In this paper we address the L∞ Voronoi diagram of polygonal objects and present applications in VLSI layout and manufacturing. We show that in L∞ the Voronoi diagram of segments consists only of straight line segments and is thus much simpler to compute than its Euclidean counterpart. Moreover, it has a natural interpretation. In applications where Euclidean precision is not particularly impor...

This paper describes an approach to the specification and modeling of information associated with the design and evolution of VLSI components. The approach is characterized by combined structural and behavioral descriptions of a component. Database modeling requirements specific to the VLSI design domain are considered and techniques t.o address them are described. An extensible object-oriented...

The reverse engineering process for VLSI chips is a complex operation that can cost from $10,000 for the simplest chips to hundreds of thousands of dollars for complex chips. In this study, we present an overview of the process of reverse engineering VLSI chips. The study outlines the steps involved in the process of reverse engineering chips as well as the different techniques used to extract ...

FPGA based VLSI processor arrays provide an enormous computation performance along with the flexibility of reconfigurable logic. In the future, hybrid processors will become available that consist of a RISC core and configurable logic area on the same die. This allows for the efficient usage of a VLSI array as a coprocessor to the RISC core. Due to their high performance, VLSI array structures ...

| The inter-wire spacing in a VLSI chip becomes closer as the VLSI fabrication technology rapidly evolves. Accordingly, it becomes important to consider crosstalk caused by the coupling capacitance between adjacent wires in the layout design for the fast and safe VLSI circuits. The upper bounds of the allowable crosstalk for nets, called cross-talk constraints, are usually given in the design s...

The introduction of systolic arrays in the late 1970s had an enormous impact on the area of special purpose computing. However, most of the work so far has been done with onedimensional and two-dimensional (2D) systolic arrays. Recent advances in three-<limensional VLSI (3D VLSI) and 3D packaging of2D VLSI components, has made the idea of 3D systolic arrays feasible in the near future. In this ...

{ Until recently, VLSI designers rarely considered yield issues when selecting a oorplan for a newly designed chip. This paper demonstrates that for large area VLSI chips, especially those that incorporate some fault tolerance, changes in the oorplan can aaect the projected yield. We study several general oorplan structures, make some speciic recommendations, and apply them to actual VLSI chips...

In this paper, the impact of gate induced drain leakage (GIDL) on the overall leakage of submicrometer VLSI circuits is studied. GIDL constitutes a serious constraint, with regards to off-state current, in scaled down complimentary metal–oxide–semiconductor (CMOS) devices for DRAM and/or EEPROM applications. Our research shows that the GIDL current is also a serious problem in scaled CMOS digit...

This chapter presents the application of Differential Evolution (DE) Algorithm for the VLSI floorplanning problems. DE Algorithm has been successfully applied to VLSI sequence pair representation. The important advantages of DE are its simplicity, fast convergence, and easy for implementation. DE algorithm is a population based algorithm like GA using similar operators such as crossover, mutati...

The performance description language PDL provides a compact notation for the speciication of non-functional attributes of VLSI systems. This paper presents evaluation mechanisms which allow the designer to assert performance goals on PDL models of VLSI systems and determine if the constrained models are satissable. This is done by developing a PDL performance model and constructing a constraint...