Asynchronous design has a potential of solving many difficulties, such as clock skew and power consumption, which synchronous counterpart suffers with current and future VLSI technologies. This paper proposes a new delay model, the scalable-delay-insensitive (SDI) model, for dependable and high-performance asynchronous VLSI system design. Then, based on the SDI model, the paper presents the des...

Advances in System-on-Chip (SoC) design have emphasized the need for driving long on-chip differential traces. The delay of long traces has traditionally been handled by inserting repeaters at periodic intervals. The repeater method reduces the delay at the expense of increased power consumption. At the same time, power is a major design consideration in SoC design, motivating a driver methodol...

Advances in System-on-Chip (SoC) design have emphasized the need for driving long on-chip differential traces. The delay of long traces has traditionally been handled by inserting repeaters at periodic intervals. The repeater method reduces the delay at the expense of increased power consumption. At the same time, power is a major design consideration in SoC design, motivating a driver methodol...

 Envisioning system-on-chip design as the next industrial evolution, the Taiwan government recently launched a national Si-Soft project aiming to improve the infrastructure for the SOC based high-tech industry in Taiwan. The fabric of the Si-Soft project is the manpower development. The potential human resources in the TVE systems are thus considered as the best supply to achieve the goal of s...

A number of innovative designs have been proposed for hardware implementation of data structures. However, these designs have only been presented at an abstract behavioural level. In this paper, we describe the VLSI design and implementation of a 15-node 8-bit queue based on a systolic tree architecture. A layout methodology and a VLSI CAD environment that facilitate fast and efficient layout o...

This paper discusses recently introduced strategies in implementing DSP systems using residue replication; in particular we highlight current work underway in the VLSI Research Group, at the University of Windsor, in the area of constructing high throughput DSP systems on silicon. The paper first briefly reviews the theory and mapping techniques, associated with general residue and residue repl...

Algorithms for the Scaling Toward Nanometer VLSI Physical Synthesis. (December 2005) Chin Ngai Sze, B.Eng., The Chinese University of Hong Kong; M.Phil., The Chinese University of Hong Kong Chair of Advisory Committee: Dr. Jiang Hu Along the history of Very Large Scale Integration (VLSI), we have successfully scaled down the size of transistors, scaled up the speed of integrated circuits (IC) a...

Power consumption of Very Large Scale Integrated (VLSI) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally dynamic (switching) power has dominated the total power consumption of VLSI circu...

OF THE DISSERTATION Process Variation Aware Interconnect Simulation and Optimization in VLSI Design

Circuit partitioning is the one of the fundamental problems in VLSI design. It appears in several stages in VLSI design, such as logic design and physical design. Circuit partitioning is generally formulated as the graph partitioning problem. Circuit partitioning problem is a well known NP hard problem. The potential of Genetic Algorithm has been used to solve many computationally intensive pro...