This paper argues that the subjective expected utility (SEU) model has serious limitations in both positive and normative analysis. In addition to experimental evidence, I discuss examples where alternatives to the SEU provide a richer framework for the study of problems of choice under uncertainty. Opportunities for improved positive and normative analysis using non-SEU models are discussed. *...

Experimental and theoretical analysis has shown that the conventional expected utility (EU) and subjective expected utility (SEU) models, which are linear in probabilities, have serious limitations in certain situations. We argue here that these limitations are often highly relevant to the work that environmental and natural resource economists do. We discuss some of the experimental evidence a...

Results were previously presented [2] from real-time experiments that evaluated large FPGAs fabricated in different CMOS technologies (0.15μ, 0.13μ and 90 nanometer) for their sensitivity to radiationinduced single-event upsets. These results were compared to circuit simulation (Qcrit) studies, as well as to LANSCE neutron beam results and Crocker Nuclear Laboratory (U. C. Davis) cyclotron prot...

Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-eventupset (SEU) immunity. The proposed latch can effectively mitigate SEU by internal dual interlocked scheme. The propagation delay, power dissipation and power delay product of the pr...

The methodology for the design and testing of fault tolerant systems implemented into an FPGA platform with different types of diagnostic techniques is presented in this paper. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance features of the digital design implemented into the SRAM-based FPGA. The methodology includes detection ...

Xilinx® devices are designed to have an inherently low susceptibility to single event upsets (SEUs). This application note provides a substantial discussion of strategies and representative calculations for handling SEUs with an emphasis on reliability when addressing these low probability events. This application note introduces an SEU controller macro that can be included in any Virtex®-5 FPG...

Technology scaling relies on reduced nodal capacitances and lower voltages in order to improve performance and power consumption, resulting in significant increase in layout density, thus making these submicron technologies more susceptible to soft errors. Previous analysis indicates a significant improvement in SEU tolerance of the driver when the bias current is injected into the circuit but ...