This paper presents a new procedure for the speed changing of the twospeed compressor driven by the singlephase Permanent Split Capacitor (PSC) motor. The use of the two-speed motor for compressor is one of the effective ways for their capacity control. But the two speed compressors now in use are driven by three-phase motors. It is because a single-phase, two-speed motor has rather a small sta...

Now a day’s reversible logic is an attractive research area due to its low power consumption in the area of VLSI circuit design. The reversible logic gate is utilized to optimize power consumption by a feature of retrieving input logic from an output logic because of bijective mapping between input and output. In this manuscript, we design 4:2 and 5:2 reversible compressor circuits using a new ...

Block based motion estimation is one of the critical task in video compression standards such as MPEG-4, H.263, H.264. The key element of the block based motion estimation algorithms is the matching criteria. SAD(Sum of Absolute Difference) is the most common matching criteria chosen in video coding because of its low complexity, good performance and ease of hardware implementation. By utilizin...

This paper gives two lossless speech compression schemes Hamming correction codes compressor (HCCC) and Systematic Linear Block Code Compressor (SLBC) based on error correcting Hamming code and systematic linear block codes respectively. Hamming codes are a family of linear errorcorrecting codes that can detect up to two-bit errors or correct one-bit errors. Systematic linear block code is any ...

A Multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, Digital Signal Processors (DSPs), Microprocessors etc., A Wallace tree multiplier is an improved version of tree based multiplier architecture. It uses 4:2, 5:2 compressors and a Carry Select Adder (CSA) to reduce the latency and power consumption. In conventional methods, 10T XNOR s...

This paper describes a new design of low power 3-2 compressor circuit for high speed multipliers. Power consumption of proposed 3-2 compressor circuit varies from 0.355 nW to 1.6964 nW and delay varies from 2.0390 ns to 2.0224 ns. Further, power delay product of proposed circuit varies from 7.23×10 -18 (J) to 34.30×10 -18 (J) with varying supply voltage from 1.8V to 3.3V. The proposed compresso...

Motivated by the increase in storage space and Internet connection speed, as well as significant improvements in audio hardware, the interest for lossless audio compression has been greatly increasing, especially in the consumer market. In this article, we present a short performance comparison of the state of the art lossless audio compressors. The focus is on the OptimFROG symmetrical compres...

Through the use of multiple-input/single-output (MISO) modeling, the propagation paths of sound within a reciprocating refrigeration compressor have been investigated and ranked. By investigating the nature of sound propagation within reciprocating compressors. it is hoped that strategies for compressor sound reduction can effectively be formulated . From experimental data of compressor far-fie...