This paper propose a new circuit design which monitor total leakage current during standby mode and generates the optimal reverse body bias voltage, by using the adaptive body bias (ABB) technique to compensate die-to-die parameter variations. Design details of power monitor are examined using simulation framework in 65nm and 32nm BTPM model CMOS process. Experimental results show the overhead ...

In this paper a comparative study of different CMOS transimpedance amplifier has been presented. Standard device parameters such as gain, input refereed noise, power dissipation and group delay are studied compared. Here the is divided on basis its topology technology used performance summarized to get overview. Most analysis taken performed 0.18 μm some implemented using 45nm, 0.13μm, 65nm, 90...

This paper describes the design of a power amplifier (PA) for 802.11n WLAN fabricated in 65nm CMOS technology. The PA utilizes 3.3V thick gate oxide (5.2nm) transistors and a twostage differential configuration with integrated transformers for input and interstage matching. A methodology used to extract the layout parasitics from electromagnetic (EM) simulations is described. For a 72.2Mbit/s, ...

77GHz CMOS radar system development project have been progressing in ETRI from June 2010. In this work, a new radar architecture so called CMOS centric topology is proposed and transceiver blocks are implemented by 65nm CMOS technology. CMOS centric architecture employing eight channel I/Q modulated receivers with fully differential signal path and minimizing the millimetre-wave circuitry for s...

A 1.2V 6mW 500MS/s 5-bit ADC for use in a UWB receiver has been fabricated in a pure digital 65nm CMOS technology. The ADC uses a 6-channel time-interleaved successive approximation register architecture. Each of the channels has a split capacitor array to reduce switching energy and sensitivity to digital timing skew. A variable delay line is used to optimize the instant of latch strobing to r...

In this paper, a 10-bit digital Correlated Double Sampling (CDS) high-speed CMOS Image Sensor designed in 65nm BSI technology for a 1.1μm pixel is proposed. The readout architecture has been developed to read a 13Mpix sensor (4248 x 3216) at 55frames/s, requiring a row time of 5.5μs. The readout is based on a Piece-Wise Linear (PWL) ramp generator implementing an I/C structure. Two innovative c...

This paper presents low power 8x8 bit multipliers which are implemented with Tanner Tool v13.0 at 500MHz frequency with 65nm technology which is having a supply voltage 1.0v. There are different CMOS multiplier circuits are analyzed names as Braun multiplier, Wallace tree multiplier, Row bypass Braun multiplier, Column bypass Braun multiplier, Row and Column bypass Braun multiplier and these mu...

This paper describes a new Bandgap Reference (BGR) architecture with low power consumption and high Power Supply Rejection Ratio (PSRR). Implemented in a 65nm CMOS technology, the circuit includes a pre-regulator, a current source and also digital validation for the bandgap voltage. The current consumption is below 4.9μA at 50oC, PSRR of -110dB@1kHz and -61.3dB@10MHz. The reference output volta...

This paper presents the design and analysis of Ultra Wideband (UWB) mixer in 65nm CMOS technology. To achieve the optimized performance, a new mixer topology is suggested. The performance parameters of the mixer viz.: conversion gain, Noise Figure, linearity and power consumption are addressed in this paper. The simulation results of the new mixer topology suggested in this paper achieves the r...