Settling time is one of the most important parameter in design of DLLs. In this paper we propose a new high speed with low settling time Delay Locked Loop (DLL) in which a digital signal processor (DSP) is used instead of using phase-frequency detector, charge pump and loop filter in conventional DLL. To have better settling time, PRP conjugate gradient algorithm is used to optimize delay of ea...

The precision of phase-locked loop (PLL) has a direct effect on the output performance for three-phase grid-connected inverter or three-phase active PFC. In this paper, a new three-phase digital closed-loop phase-locked algorithm is proposed on the basis of synchronous reference frame transformation. Synchronous simulation of the PLL techniques is a good choice even if the polluted three-phase ...

Design and simulation of Digital PLL has been illustrated in this paper. The Digital PLL is given signal of 400 MHz to 900 MHz in the UNII (Unlicensed National Information Infrastructure) lower band which is used by IEEE 802.11(a). All the Digital PLL blocks are designed and simulated using Simulink. It is verified that Digital PLL is stable with a phase margin of 91.1 degree which satisfy the ...

Zero Crossing Digital Phase Locked Loop with Arc Sine block (AS-ZCDPLL) is used to linearize the phase difference detection, and enhance the loop performance. The loop has faster acquisition, less steady state phase error, and wider locking range compared to the conventional ZCDPLL. This work presents a Zero Crossing Digital Phase Locked Loop with Arc Sine block (ZCDPLL-AS). The performance of ...