This paper presents a design method of SAR ADC (Successive Approximation Register Analog-to-Digital Converter ADC) utilizing redundancy bits. In general, binary search algorithm is used as a conventional SAR ADC operation algorithm. It’s possible to realize a high-speed SAR ADC by using non-binary search algorithm which is realized by adding redundancy bits. However, the A/D conversion time var...

This paper presents the modeling and simulation of a 833.33 kS/s, 51.279μW successive approximation register(SAR) Analog to Digital Converter(ADC) using 0.18μm CMOS technology that uses internally generated signal for approximation for low power applications. The ADC is powered by single supply voltage of 1V. In our scheme, comparator output time and bit settling time of the Digital to Analog C...

Proof-of-concept cyclic analog-to-digital converters (ADCs) have been designed and fabricated in 90-nm CMOS technology. The measurement results of an experimental prototype demonstrate the effectiveness of the proposed switched-capacitor (SC) architecture to realize a non-binary ADC based on β expansion. Different from the conventional binary ADC, a simple 1-bit/step structure for an SC multipl...

An analog queue-based architecture and an adaptive digital-calibration algorithm calibrate an 8-bit two-stage pipelined algorithmic analog-to-digital converter (ADC). To minimize power dissipation and noise, the queue consists of only one sample-and-hold amplifier. At a sampling rate of 20 Msamples/s, the peak signal-to-noise-and-distortion ratio (SNDR) is 45 dB, and the spurious-free dynamic r...

Efficient Analog-Digital Converters (ADC) are one of the mainstays of mixed-signal integrated circuit design. Besides the conventional ADCs used in mainstream ICs, there have been various attempts in the past to utilize neuromorphic networks to accomplish an efficient crossing between analog and digital domains, i.e., to build neurally inspired ADCs. Generally, these have suffered from the same...

This paper proposes a generic algorithm for k-bit Analog to Digital Conversion. The proposed algorithm is very fast method of conversion of an analog signal into k-bit digital output in a multi-bit parallel fashion. The algorithm employs m stages, each of which is capable of producing bits such that k/m bits are converted at the same time. Thus, this algorithm can be considered a k = n X m conv...

This paper presents an energy efficient successive-approximation register (SAR) analog-to-digital converter (ADC) for low-power applications. To improve the overall energy-efficiency, a skipping-window technique is used to bypass corresponding conversion steps when input falls in window indicated by time-domain comparator, which can provide not only polarity of input, but also amount informatio...

A new high-resolution and high-speed fully differential Successive Approximation Register (SAR) Analog to Digital Converter (ADC) based on Capacitor Merged Technique is presented in this paper. The main purposes of the proposed idea are to achieve high-resolution and high-speed SAR ADC simultaneously as well. It is noteworthy that, exerting the suggested method the total capacitance and the rat...

Analog-to-digital conversion (ADC) has been widely studied as a key interface technology to connect continuous analog signals and manageable digital signals. Recent tremendous growth of high-speed digital signal processing and communication systems has encouraged the demand for a high-speed ADC. For the realization of a high-speed ADC, optical approaches have much attracted recently [1]. ADC co...

This paper presents a multi-mode receiver concept for different transmission standards like UMTS and IS95. Due to the use of a Digital-Front-End (DFE) the requirements for the analog part of the well known direct conversion receiver (DCR) architecture decrease because channelization and fine frequency tuning are shifted from the analog into the digital domain. The adaptation of the channelizati...