This paper proposes a test cost prediction model which estimates the cost of IC testing in a manufacturing environment. The model predicts chip testing cost and quality of test using a set of circuit manufacturing parameters. The objective is to use these circuit parameters which are available at the early stage of the design cycle to determine and optimize manufacturing test cost.

This paper presents an envisaged autonomous strain sensor device, which is dedicated to structural health monitoring applications. The paper introduces the ASIC approach that replaces the discrete approach of some of the main modules.

Key Laboratory for Low Dimensional Materials and Application Technology of Ministry of Education (Xiangtan University), Xiangtan, Hunan 411105, China ASIC R&D Center, School of Electronic Science and Engineering of National University of Defense Technology, Changsha, Hunan 410073, China Pacific Geoscience Centre, Geological Survey of Canada, 9860 West Saanich Road, Sidney, British Columbia, Can...

We describe the use of hardware compilation techniques to provide a exible interfacing and computing platform for building self-validating (SEVA) sensors. SEVA technology has been developed at Ox-ford as a generic method of supplying a real-time guarantee on the quality of a physical measurement as well as the measurement itself. We describe the reconngurable hardware platforms that have been c...

Bargaining with reading habit is no need. Reading is not kind of something sold that you can take or not. It is a thing that will change your life to life better. It is the thing that will give you many things around the world and this universe, in the real world and here after. As what will be given by this closing the power gap between asic custom tools and techniques for low power design, ho...

Robust, high yield IC design requires statistical simulation, and therefore statistical models. Simple “fast” and “slow” sets of model parameters are not sufficient to predict the manufacturing variations of all measures of circuit performance for arbitrary circuit topologies, device geometries, and biases. This paper describes an accurate and efficient approach to statistical modeling and char...

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Power-Performance Tradeoffs In ASICs for Next Generation Wireless Communication Datapaths

Welcome and Opening 8:30-8:40 Opening Remarks Adrian Evans IROC 8:40-8:50 Clereco Project Overview Stefano Di Carlo Politecnico di Torino 8:50-9:00 MoRV Project Overview Domenik Helms OFFIS Session I – Invited Talks Chair : Dimitris Gizopoulos – University of Athens 9:00-9:45 The Resilience Wall: CrossLayer Solutions Subhasish Mitra Stanford University 9:45:10:30 Reliability Challenges for Larg...

If you look at the mix of papers published at ITC over the last ten years or so, there does appear to be a large swing away from board test topics and towards more IC-oriented technical papers. Why is that? Could one argue that board test became a solved problem after the introduction of the IEEE 1149.1 standard [1]? Hardly, since that original standard, as useful as it has proven to be, was st...