MSC 2000: 93A10, 93D05, 93D15

Power reduction is one of the main reasons for designing asynchronous circuits. Asynchronous circuits are inherently capable of having low power consumption. In this paper, we introduce five methods to achieve even lower power consumption. We have applied these methods to some sample circuits and the experimental results show that power reduction of 20% to 41% is obtainable.

Most asynchronous processor Instruction Set Architectures (ISA) are based on a single type of underlying asynchronous circuit design style. Asynchronous processor ISAs are entirely dependent on the type of asynchronous design style chosen and can support a limited set of simple applications only. Design reuse is typically difficult to realize in such cases. In this paper, we show a behavioral m...

As the number of transistors on a single integrated circuit approach a billion, the problems of clock distribution, power consumption, multiple clock domains, meeting timing requirements, and reuse of subsystem designs grow ever more difficult. Coordinating a billion transistors with the present design methodologies will require hundreds of years of engineering time. A new design methodology is...

Specification for circuit usually trys to accomplish certain goals. Examples: Protocol never deadlocks. Whenever there is a request, it is followed by an acknowledgement possibly in a bounded amount of time. Can check by simulating a number of important cases. Simulation does not guarantee correctness of the design. Big problem in asynchronous design where a problem only manifests under a very ...

A new multiple-valued current-mode (MVCM) integrated circuit based on dual-rail differential logic, whose currentdriving capability is high at a low supply voltage, is proposed to realize a totally self-checking circuit and an asynchronous-control circuit. Two nMOS transistors with different threshold voltages are used as complementary pass switches in the proposed differential-pair circuit (DP...

Remarkable advantages of asynchronous circuits in comparison with their synchronous counterparts results in vast effort in designing such circuits. This paper proposes optimized asynchronous circuit design approach by exploiting potent evolutionary circuit design method. The evolutionary algorithm applies fast and accurate hazard detection technique as a fitness function. Outcomes of proposed m...

An asynchronous circuit, or self-timed circuit, is a sequential digital logic circuit which is not enabled by a global clock signal. Instead of that, they often use signals that indicate completion of operations and instructions, specified by handshaking or simple data transfer protocols. This type is contrasted with a synchronous logic circuit where changes to the output signal values are trig...

In this paper, we demonstrate the formal verification of a practical timed asynchronous circuit. The target circuit is obtained by abstracting the instruction cache subsystem of a real asynchronous processor, TITAC 2. We also show several techniques to improve our verification method. The improved verifier could verify the target circuit in approximately 15 minutes, using less than 20 MBytes of...

The implementation of a low power logic based asynchronous circuit with the help of power gated logic. In asynchronous power gated logic (APL) circuit, each pipeline stage was incorporated with efficient charge recovery logic (ECRL) gate; handshake controller and partial charge reuse (PCR) mechanism. The main objective was, to provide a new lower power solutions using power gating (PG) for very...