We investigate signal-to-noise ratio (SNR) characteristics of an 850-nm optoelectronic integrated circuit (OEIC) receiver fabricated with standard 0.25-µm SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. The OEIC receiver is composed of a Si avalanche photodetector (APD) and BiCMOS analog circuits including a transimpedance amplifier with DC-balanced buffer, a tunable e...

A large dynamic-range Variable Gain Amplifier (VGA) suitable for Ultra Wide Band (UWB) applications is presented. The VGA is composed of three programmable variable gain amplifier stages followed by an output buffer. Such wide bandwidth allows our proposed VGA to be used in multi-standard protocols. Power reduction is developed for the variable gain amplifier stages. Thorough analyses of the mi...

An ultra low-power high-speed rail-to-rail buffer amplifier with improved current summing circuit is proposed for LCD source drivers. By placing two complementary differential pairs in parallel, it is possible to obtain a rail-to-rail input stage. Then, a current summing circuit with two embedded comparators is proposed. With the proposed current summing circuit, the output stages will be turne...

A CMOS realization of the current-feedback differential difference amplifier (CFDDA) is proposed. The CFDDA circuit is realized using a wide input range dependent load transconductor (DTA) with three independent input voltages and a rail to rail classAB voltage buffer. The CFDDA circuit is used to realize a MOS-C oscillator suitable for VLSI. PSpice simulation results for the CFDDA circuit and ...

This paper proposes a new MPEG-4 rate control algorithm for single or multiple object video sequences. The algorithm aims to achieve an accurate bit rate with the maximum picture quality while efficiently handling buffer fullness and scene change. In addition to estimating the bit budget of a frame based on its global coding complexity, the algorithm dynamically distributes the target bits for ...

A high performance and buffer amplifier for liquid crystal display system is presented here. The proposed architecture contains self biased RAIL TO RAIL complementary differential pair , and class B output driving stage which is suitable for large and small size liquid crystal display, compensation capacitor and resistance are used to improve the settling time and slew rate of the buffer amplif...

A current reused low-noise amplifier (LNA) with gain compensated to extend the bandwidth and is designed for ultra-wideband (UWB) wireless receiver. The design consists of two cascode common-source amplifier and an output buffer which is implemented in 0.18um RF CMOS process. The LNA gives 13.1dB gain; 9.1GHz 3dB bandwidth (3.1-12.2GHz) while consuming 13.9mW through a 1.8V supply. Over the 3.1...

A class-AB rail-to-rail CMOS buffer amplifier is proposed and fabricated. The main circuit structure includes a bias circuit, a complementary folded-cascode differential input stage, a common-mode rejection ratio (CMRR) enhancement stage, and a class-AB output stage. With the complementary folded-cascode input stage, high input common-mode range (ICMR) and rail-to-rail output are realized. By u...

In this paper, a low parasitic capacitance and low-power CMOS capacitive fingerprint sensor readout circuit is presented. The side effect of parasitic capacitance has been under control with novel layout structure in sensor cell, and minimal size switch is used to reduce non-ideal effects of MOS switch and achieve good linearity. Power dissipation is also reduced with quiescent current control ...

Class-AB circuits, which are able to deal with currents which are orders of magnitude larger than their quiescent current, are good candidates for low-power analog design. This paper presents a new, simple, class-AB current-mirror, based on the Flipped Voltage Follower [1]. In the authors knowledge this is the first class-AB currentmirror which operates with a supply voltage smaller than two tr...