Floating point sparse matrix vector multiplications (SM×V) are kernel operations for many scientific algorithms. In these algorithms, the SM×V is often responsible for the biggest part of the processing time. It is thus important to speed-up the processing of the SM×V. To use an FPGA to do this is a logical choice since FPGAs are inherently parallel. The core operation of the SM×V is to reduce ...

Background/Objectives: Density, performance, and design complexity of integrated circuits are rapidly increasing specifically in 3-D integration where multi-plane synchronization is required. The power clock distribution networks consume a large portion the limited on-chip metal resources. In order to reduce overhead associated with power, global clock, local networks, concept an network (IPCDN...

In this work, we demonstrate a novel carrier transporting combination made of tungsten trioxide (WO3) nanomaterials and Cs2CO3/PCBM buffer bilayer for the fabrication of perovskite solar cells (PSCs). Two different types of WO3, including nanoparticles and nanorods, were prepared by sol-gel process and hydrothermal method, respectively. Cs2CO3/PCBM buffer bilayer was inserted between WO3 and pe...

A switched capacitor circuit which simulates Frequency Dependant Negative Resistor is proposed. The circuit is controlled by three phases clock and needs one unity gain buffer. A comparison among SC FDNRs in other references is shown. SWITCAP simulation of SC filter using these circuits are also shown. Key-Words; Switched-Capacitor(SC) Frequency Dependant Negative Resistor(FDNR) Filter immittan...

For the recent CMOS feature sizes power dissipation becomes an overriding concerns for VLSI circuit design. We propose a novel approach named tri-state elastic buffer design which reduces the total power, area & delay of elastic buffer. The paper presents a design and implementation of tristate buffer mechanism in 120 nm technology. This design offers also the advantage of third state (High Imp...

In this paper we study the quality of service of integrated voice and data services in a wireless network. The voice traffic is transmitted in circuit-switched mode and data traffic is transmitted in packetswitched mode. We apply a fluid analysis to study the performance of the data buffer under two handoff schemes and the basic system. From this analysis, we derive admission controls for voice...

this paper proposes a buffer circuit for footed domino logic circuit. It minimizes redundant switching at the output node. This circuit prevents propagation of precharge pulse to the output node during precharge phase which saves power consumption. We have calculated the power consumption, delay and power delay product of proposed circuits and compared the results with existing domino circuit f...