نتایج جستجو برای: clocking
تعداد نتایج: 739 فیلتر نتایج به سال:
Communication between independently-clocked digital subsystems typically involves a nite probability of synchronization failure whose minimization introduces delays and consequent performance costs. This paper explores a technique that eliminates both the inherent unreliability of such communication and the performance overhead it implies. Our approach maintains a known phase relationship betwe...
This paper enumerates a low power, high speed design of flip-flop having less number of transistors. In flip-flop design only one transistor is being clocked by short pulse train which is known as True Single Phase Clocking (TSPC) flip-flop. The true single-phase clock (TSPC) is common dynamic flip-flop which performs the flip-flop operation with little power and at high speeds. In this paper, ...
This paper introduces a distributed approach to interleaving paralleled power converter cells. Unlike conventional methods, the distributed approach requires no centralized control, automatically accommodates varying numbers of converter cells, and is highly tolerant of subsystem failures. A general methodology for achieving distributed interleaving is proposed, along with a specific implementa...
A detailed numerical simulation of the free charge trsnrfer in overlapped gate charge-coupled devices (CCD) is presented. The transport dynamics are analyzed in terms of thermal diffusion, self-induced fields, and fringing fields under all the relevant electrodes and the interelectrode regions with time-varying gate potentials. The results of the charge trmwfer with clifferent clocking schemes ...
A critical problem in building long systolic arrays lies in efficient and reliable synchronization. We address this problem in the context of synchronous systems by introducing probabilistic models for two alternative clock distribution schemes: tree and straight-line clocking. We present analytic bounds for the Probability of Failure and the Mean Time to Failure, and examine the trade-offs bet...
Clocking considerations and clocked storage elements for System on a Chip are discussed. Various ways of SOC clocking are addressed. We discuss issues of particular importance for SOC such as “time borrowing” and absorption of clock uncertainties. Clock power savings techniques suitable for SOC are described.
An interface for MEMS gyroscope is implemented in 0.18μm HVCMOS technology, and achieves a low noise floor of 1m°/sec/ Hz over 200Hz BW. Electromechanical forcefeedback and self-clocking scheme based on gyro resonance are implemented. The interface includes on-chip reference generation, decimation, and temperature compensation. Keywords-gyroscopes; Sigma delta modulation; Force feedback; Self-c...
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