A single-stage 24 GHz triple stacked power amplifier using 0.13 μm CMOS process is demonstrated. To Compare with parallel current combining method, series voltage combining method using a stacked amplifier architecture can realize a large output voltage swing from the top transistor without exceeding the transistor breakdown voltage limitations. However, at high frequencies, parasitic capacitan...

Current comparator is a fundamental component of current-mode analog integrated circuits. A novel high-performance continuous-time CMOS current comparator is proposed in this paper, which comprises one CMOS complementary amplifier, two resistive-load amplifiers and two CMOS inverters. A MOS resistor is used as the CMOS complementary amplifier’s negative feedback. Because the voltage swings of t...

In this paper, a CMOS Multi-band LNA using High-Q active inductors load with a binary code band selector suitable for multi-standards wireless applications is proposed. Using an improved high-Q active inductor including two bits binary controlled code, the multi-band low noise amplifier operating at four different frequency bands is realized. The proposed amplifier is designed in TSMC 0.18-um C...

This paper presents the design of a high efficiency, low THD, 5.7GHz fully differential power amplifier for wireless communications in a standard 0.18μm CMOS technology. The power amplifier employs a fully differential class-E topology to achieve high power efficiency by exploiting its soft-switching property. In order to achieve high operating frequency, an injectionlocked oscillator is utiliz...

A low-noise CMOS amplifier operating at a low supply voltage is developed using the two noise reduction techniques of autozeroing and chopper stabilization. The proposed amplifier utilizes a feedback with virtual grounded input-switches and a multiple-output switched opamp. The low-noise amplifier fabricated in a 0.18-μm CMOS technology achieved 50-nV/ √ Hz input noise at 1-MHz chopping and 0.5...

We have proposed a 2 GHz CMOS Differential Low Noise Amplifier (LNA) for wireless receiver system. The LNA is fabricated with the 0.18 μm standard CMOS process. Cadence design tool Spectre_RF is used to design and simulation based on resistors, inductors, capacitors and transistors. Power constrained methodology is used for the design of Differential Low Noise Amplifier. Consuming 9mA current a...

A novel low noise trans-impedance amplifier is proposed using low cost 0.18 µm CMOS technology. A resistive-capacitive feedback is used to extend the bandwidth of the amplifier. As the structure is inductor less, it is suitable for low cost integrated optical interconnects. In this paper Improved Particle Swarm Optimization have applied to determine optimal trans-resistance and noise of propose...

in this study an ultra-broad band, low-power, and high-gain cmos distributed amplifier (cmos-da) utilizing a new gain-cell based on the inductively peaking cascaded structure is presented. it is created bycascading of inductively coupled common-source (cs) stage and regulated cascode configuration (rgc).the proposed three-stage da is simulated in 0.13 μm cmos process. it achieves flat and high ...

This paper presents the design of a CMOS RF Power Detector (PD) using 0.18 μm standard CMOS technology. The PD is an improved unbalanced source coupled pair incorporating an output differential amplifier and sink current steering. It realizes an input detectable power range of −30 to −20 dBm over 0.1–1 GHz. Also it shows a maximum data rate of 30 Mbps with 2 pF output loading under OOK modulati...

Bluetooth Low Energy (BLE) is an advanced technology that has been designed as complementary technology to classic Bluetooth and also it is the lowest possible power wireless technology that can be designed and built. This paper provides an overview of bluetooth low energy technology and utilization of CMOS Low Noise Amplifier (LNA) for BLE applications. The aim of this paper is review and comp...