Test scheduling is crucially important for optimal SoC test automation in allocating the limited available test resources. To assign test resource, this paper introduces a fuzzy based engine. Test pipelining is used to minimize the time of testing the SoC. The power consumption during the test process should be under control, without exceeding the maximal power and damaging the whole systems. C...

We present optimal solutions to the test scheduling problem for core-based systems. We show that test scheduling is equivalent to the m-processor open-shop scheduling problem and is therefore NP-complete. However, a commonly-encountered instance of this problem (m = 2) can be solved in polynomial time. For the general case (m > 2), we present a mixed-integer linear programming (MILP) model for ...

Modeling human behavior requires vast quantities of accurately labeled training data, but for ubiquitous people-aware applications such data is rarely attainable. Even researchers make mistakes when labeling data, and consistent, reliable labels from low-commitment users are rare. In particular, users may give identical labels to activities with characteristically different signatures (e.g., la...

In just a few years, cores have become an integral part of the design process for system-on-a-chip products. It is not hard to see why; today’s gate capacities in the millions are well beyond the capabilities of most design teams. The effective use of such large capacities suggests, even demands, the ability to reuse existing designs. Some companies have developed effective techniques and proce...

| This tutorial responds to the rapidly increasing use of various cores for implementing systems-on-a-chip. It speci cally focusses on processor cores. We will give some examples of cores, including DSP cores and application-speci c instruction-set processors (ASIPs). We will mention market trends for these components, and we will touch design procedures, in particular the use compilers. Finall...

– Core-based testing, which is described by the proposed IEEE standard P1500, is an effective test method for Systems-on-Chip (SOC) containing embedded cores. This test method is usable for all classes of digital cores and provides solutions that allow automatic identification and configuration of testability features in SOC containing embedded cores. In this moment, IEEE P1500 is restricted to...

A wrapper is a thin shell around the core, that provides the switching between functional, and core-internal and core-external test modes. Together with a test access mechanism (TAM), the core test wrapper forms the test access infrastructure to embedded reusable cores. Various company-internal as well as industry-wide standardized but scalable wrappers have been proposed. This paper deals with...