We present a framework for high-level design validation using an efficient register-transfer level (RTL) automatic test pattern generator (ATPG). The RTL ATPG generates the test environments for validation targets, which include variable assignments, conditional statements, and arithmetic expressions in the HDL description. A test environment is a set of conditions that allow for full controlla...

In this paper, we consider the problem of Local Register Allocation (LRA): given a sequence of instructions (basic block) and a number of general purpose registers, nd the schedule of variables in registers that minimizes the total tra c between CPU and the memory system. Local register allocation has been studied for more than thirty years in the theory and compiler communities. It was not kno...

Software watermarking involves embedding a unique identifier within a piece of software, to discourage software theft. The global revenue loss due to software piracy was estimated to be more than $50 billion in 2008. We survey the proposed register allocation based algorithms for software watermarking. This family of static watermarks are constraint-based and embed the watermark in a solution t...

A retrospective evaluation of attitudinal, behavioural and knowledge change among diverse stakeholder groups was conducted in Limpopo Province of South Africa to assess the effectiveness of a series of values clarification (VC) interventions. Telephone and face-to-face interview (193) results revealed that over two-thirds (70.2%) reported behavioural changes and 93.2% reported increased compass...

Today, with the development of GPU computing techniques in terms of architectures and hardware and software support, people realized that intensive computing workload could be ported to GPU device. Applications could exploit GPUs’ characteristics for parallel computing and gain a significantly high speedup comparing to CPU architecture. However, failures are still unavoidable. People have alrea...

Abstract In the past, a scheme of Adaptive Branch Trees (ABT) has been proposed for adaptively keeping track of alternative branch paths and to speculatively execute the code on the most likely path with constrained hardware resources. In this paper, we combine the ABT concept with the instruction prefetch by realizing an ABT table to prefetch the most likely path of execution stream codes so a...

To keep up with a large degree of ILP, Itanium2 L2 cache system uses a complex organization scheme: load/store queues, banking and interleaving. In this paper, we study the impact of this cache system on memory instruction scheduling. We demonstrate that for scientific codes, “memory access vectorization” allows to generate very efficient code (up to the maximum of 4 loads per cycle). The impac...

=A design flow with register-transfer-level (RTL) partitioning and a RTL partitioning algorithm for efficient logic synthesis and layout are described in this paper. Changing the parameter of partitioning optimization dynamically, the algorithm improves an interconnection cost in a short CPU time. Experimental results on large circuits show that the algorithm partitioned circuits with the large...

Redundant number systems (RNS) are a well-known technique to speed up arithmetic circuits. However, in complete CPU, circuits using RNS were only included on subcircuit level e.g. inside the Arithmetic Logic Unit (ALU) for realization of division. Still, extending this approach create CPU with data path based can be beneficial speeding processing, due avoiding conversions ALU between and binary...

This paper presents the results of an investigation of employing configurable scalar and vector coprocessors to accelerate the G.723.1 and the G.729A speech coders. Architecture exploration has produced a reduction by up to 70% of the total number of instructions executed following the introduction of custom instructions. The accelerators are designed to be attached to a configurable embedded R...