This paper presents, a new current mode four-quadrant CMOS analog multiplier/divider based on dual translinear loops. Compared with the previous works this circuit has a simpler structure resulting in lower power consumption and higher frequency response. Simulation results, performed using HSPICE with 0.25um technology, confirm performance of the proposed circuit.

In this paper, a new approach for design of a fully differential second order current mode continuous-time sigma-delta modulator is presented. For circuit implementation, square root domain (SRD) translinear loop based on floating-gate MOS transistors that operate in saturation region is employed. The modulator features, low supply voltage, low power consumption (8mW) and high dynamic range (55...

A novel compact ultra-wideband (UWB) in-phase multilayer slotline power divider with high isolation is presented as a complement in slotline power divider field. The new structure proposed in this paper overcomes the shortcoming that power divider based on slotline almost cannot obtain high isolation between output ports. Based on the equivalent-circuit of microstrip-to-slotline transition and ...

In this article, a static frequency divider based on folded MOS current mode logic (FMCML) is presented. The design alternating FMCML flip-flops with complementary pMOS or nMOS input differential pairs since common-mode problems arise by using only one type of flip-flops. carried out after detailed theoretical modeling and analysis versus the flip-flop bias current, thus allowing defining optim...

A high accurate and low-voltage analog CMOS current divider which operates with a single power supply voltage is designed in 0.18µm CMOS standard technology. The proposed divider uses a differential amplifier and transistor in triode region in order to perform the division. The proposed divider is modeled with neural network while TLBO algorithm is used to optimize it. The proposed optimiza...

A high accurate and low-voltage analog CMOS current divider which operates with a single power supply voltage is designed in 0.18µm CMOS standard technology. The proposed divider uses a differential amplifier and transistor in triode region in order to perform the division. The proposed divider is modeled with neural network while TLBO algorithm is used to optimize it. The proposed optimiza...

A programming technique for controlling the floating gates (FG) in ultra low-voltage (ULV) floating-gate circuits is presented. Simple ultra low-voltage floatinggate current scaling and level shifting circuits are discussed. The current scaling and level shifting are accomplished using only minimum sized transistors and floating capacitors. Floating-gate current multiplier and divider circuits ...