Gate depletion and boron penetration through thin gate oxide place directly opposing requirements on the gate engineering for advanced MOSFET’s. In this paper, several important issues of deep-submicron CMOS transistor gate engineering are discussed. First, the impact of gate nitrogen implantation on the performance and reliability of deep-submicron CMOSFET’s is investigated. The suppression of...

We have demonstrated high-performance deep-submicron inversion-mode InGaAs MOSFETs with gate lengths down to 150 nm with record Gm exceeding 1.1 mS/μm. Oxide thickness scaling is performed to improve the on-state/off-state performance and Gm is further improved to 1.3 mS/μm. HBr pre-cleaning, retro-grade structure and halo-implantation processes are first time introduced into III-V MOSFETs to s...

One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key parameters affecting performance of integrated circuits [1]. Although scaling made controlling extrinsic variability more complex, nonetheless, the most profound reason for the future increase in parameter variability is that the technology is approaching the regime of funda...

This paper deals with the design opportunities of Static Random Access Memory (SRAM) for lower power Consumption and propagation delay .Here we have analyzed both read margin for read ability and write margin for SRAM write ability. Static Noise Margin affects both read margin and write margin. We have analyzed the Static Noise Margin using traditional butterfly method which requires the rotati...

This paper presents a fast polynomial approximation algorithm for constructing the Steiner tree of minimum total cost (the cost of the edge (i; j) equal to the rectilinear distance between these nodes) with diierent requirements on delays along each path to destination. The exibility of the proposed algorithm permits to drive the number of Steiner nodes in the solution without increasing the tr...

The high leakage current in deep submicron regimes is becoming a significant contributor to the power dissipation of CMOS circuits as the threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for the estimation and reduction of leakage power, especially in the low power application...