In this paper it has been demonstrated that a shielded channel made by varying the side gate length in silicon-on-nothing junctionless transistor not only improves short effect but also improve performance of CMOS circuits device. The proposed device dual stack silicon on nothing (SCDGSSONJLT) drain induced barrier lowering (DIBL), cut-off frequency and subthreshold slope are improved 20%, 39% ...

A triple metal double gate (TM-DG) MOSFET with high-k dielectrics has been proposed to overcome the short channel effects. We are using top and bottom metal gates with different work functions to screen the effect of drain (DIBL effect). It has been found that this is effective in reducing the short channel effects. The metal gates have been used to remove the poly silicon depletion of conventi...

This paper explains the performance analysis of Gate-AllAround silicon nanowire with 80nm diameter field effect transistor based CMOS based device utilizing the 45-nm technology. Simulation and analysis of nanowire (NW) CMOS inverter show that there is the reduction of 70% in leakage power and delay minimization of 25% as compared with 180 nm channel length.Gate-All-Aorund (GAA) configuration p...

Compact models of short channel effect in symmetric and asymmetric double gate MOSFETs are developed by solving two-dimensional (2-D) Poisson’s equation as a boundary value problem in the subthreshold region. The subthreshold current is obtained through the 2-D analytic potential distribution function. Threshold voltage rolloff, drain induced barrier lowering (DIBL) and subthreshold slope degra...

In this work, we investigate the performance of 18nm gate length AlInN/GaN Heterostructure Underlap Double Gate MOSFETs, using 2D Sentaurus TCAD simulation. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to large twodimensional electron gas (2DEG) density and high velocity, the maximal drain current density achieved is very high. Extensive devic...

We optimized a RODOS (reverse-order source/drain formation with double offset spacer) structure in terms of the gate delay (CV/I) and the switching energy (CV). Simulations confirmed that the poly-Si depletion effect, the DC characteristics, the gate delay and the switching energy were enhanced. In the case of 50-nm nMOSFETs, they showed a 794-μA/μm on-current, a 0.1-nA/μm off-current, a 65-mV/...

We report an SRAM with a 90% reduction of activeleakage power achieved by controlling the supply voltage. In our design, the supply voltage of a selected row in the SRAM goes up to 1 V, while that in other memory cells that are not selected is kept at 0.3 V. This suppresses active leakage because of the drain-induced barrier lowering (DIBL) effect. To avoid unexpected flips in the memory cells,...