The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF) imaging has been designed and tested. To obtain a space efficient design over 64 × 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals ...

This paper addresses some fundamental issues relating to the design of systems on chip that utilize optical interconnects. We present an information theoretical model for assessing trade-offs between global and local partitions in these systems, and evaluate interconnect topology synthesis and application mapping techniques for digital signal processing (DSP) applications in these systems.

Third-generation cellular infrastructure requires extremely high-performance signal processing in the baseband receiver. Currently, chip rate processing is implemented using FPGA and ASIC technology. The use of a digital signal processor is explored for UTRA FDD systems with the goal of reducing cost and increasing flexibility. By combining chip rate and symbol rate processing within a single p...

We propose an effective adaptive null-forming scheme for two nearby microphones in endfire orientation that are used in digital hearing aids and in many other hearing devices. This adaptive null-forming scheme is mainly based on an adaptive combination of two fixed polar patterns that act to make the null of the combined polar pattern of the system output always be toward the direction of the n...

Matched-filter is widely used in real time signal processing, especially in Radar Signal Processing. This paper provides a novel structure of digital matched-filter used in tracking radar system. This design applies block-floating-point arithmetic to improve the precision. The whole digital matched-filter is implemented in only one chip of FPGA. This ASIC has two work modes: 512 points pulse co...

A DS-CDMA demodulator uses analog sampled-data signal processing to achieve a 75-mW power dissipation and a 128-MS/s processing rate in a 1.2m double-metal double-poly CMOS process. To demodulate the signal, a low-power passive correlation technique is introduced that eliminates the integrating opamp with its associated power and settling time overhead. In a prototype demodulator, six 64-chip c...

AUTO-CALIBRATION has been used in monolithic ADCs to extend the limits of accuracy and stability imposed bl processing, packaging, temperature, and aging’.’. This paper describes a self-calibrating. 18-bit. serial-output. lOOksps ADC which is implemented on two chips: a ?BV BiCMOS analog chip, and a 5V 2@ CMOS digital chip. This partitioning allows a larger input signal for better dynamic range...

the article introduces cyclic dilation groups and finite affine groups for prime integers, and  as an application of this theory it presents a unified group theoretical approach for the  cyclic wavelet transform (cwt) of prime dimensional periodic signals.

This paper describes a programmable fuzzy controller chip designed with mixed-signal IC techniques. Its input and output signals are analog to directly interact with the information from the real world. The programmability interface is digital and the output signal is also given in digital format to allow easy embedding into digital processing environments. Experimental results from a prototype...