ni-w coatings, compared to pure nanocrystalline ni, exhibit higher hardness and wear resistance. in some cases, these coatings are considered as environmental friendly alternatives for hard chromium coating. till now, most of ni-w coatings have been produced by direct current electrodeposition from alkaline baths. in this study square pulse current was used for deposition of ni-w precipitates f...

So far, pentazocine iontophoresis has never been studied, although pentazocine is widely used in pain management. The purpose of this study was to determine whether pentazocine transportation through a cellophane membrane could be enhanced using square-wave alternating current (AC) iontophoresis with an adjusted duty cycle and dependence on the voltage and the duty cycle. Voltages of 10, 25 and...

Muscles are the final effectors of behavior. The neural basis of behavior therefore cannot be completely understood without a description of the transfer function between neural output and muscle contraction. To this end, we have been studying muscle contraction in the well-investigated lobster pyloric system. We report here the mechanisms underlying stabilization of temporally summating contra...

Wireless sensor networks demand energy efficient and application specific medium access control protocol when deployed in critical areas which are not frequently accessible. In such areas, the residual energy of nodes also become important along with the efficient data delivery. Many techniques using adaptive duty cycle approach are suggested by researchers to improve the data delivery performa...

The digital PWM modulator circuit is capable of varying the duty cycle of the output (PWM) according to the digital input word. A digitally controlled current starved pulse width modulator is described. The current from the power grid to the ring oscillator is controlled by a header circuit. By changing the header current, the pulse width of the switching signal generated at the output of the r...

In High speed operations the duty cycle of the clock signal is to bé calibrated at 50%. But the variations in process, voltage and temperature (PVT) influences the duty cycle and make it difficult to calibrate the duty cycle at 50%. To overcome this deviation Pulse width control loops (PWCLs) are used. This work presents a high performance and fast locking all digital pulse width control circui...

A 3–8 GHz delay-locked loop (DLL) with cycle jitter calibration is presented. To lower the operation frequency of a voltage-controlled delay line (VCDL), this DLL adopts the dividers, an edge combiner, and the multiple VCDLs. A duty cycle correction circuit is presented to maintain the output duty cycle of 50%. This DLL has been fabricated in 90-nm CMOS process. The measured peak-to-peak jitter...

Bandpass channel filtering is shown to attenuate both random and determinstic jitter components in high frequency clock signals. A fully differential, tunable LC bandpass filter is developed and employed to reduce Gaussian and sinusoidal distributed jitter and duty cycle distortion.