Table 2: Percent a b o ve optimum of Elmore delay to a single critical sink and wire length for three Steiner tree constructions cost comparison is with 1-Steiner. Averages were taken over 200 random nets for each net size. 4.2 Elmore-Optimality of Generic" SERT Algorithm The counterexample in Section 3.3 showing that BB-SORT is not always optimal was carefully constructed by hand; even then, B...

The problem of ordering and sizing parallel wires residing in a single metal layer within an interconnect channel is addressed in this paper. Wires are ordered such that cross-capacitances between neighboring wires are optimally shared for circuit delay minimization. Using an Elmore delay model including cross capacitances, an optimal wire ordering is uniquely determined, such that average sign...

computation of the second order delay in rc-tree based circuits is important during the design process of modern vlsi systems with respect to having tree structure circuits. calculation of the second and higher order moments is possible in tree based networks. because of the closed form solution, computation speed and the ease of using the performance optimization in vlsi design methods such as...

Moments of the impulse response are widely used for interconnect delay analysis, from the explicit Elmore delay (the first moment of the impulse response) expression, to moment matching methods which creates reduced order trans-impedance and transfer function approximations. However, the Elmore delay is fast becoming ineffective for deep submicron technologies, and reduced order transfer functi...

those of the MST and AHHK 1] constructions for nets of up to 17 pins using the same IC parameters. All delays in the table are calculated using the Two-Pole simulator. The AHHK algorithm of Alpert et al. is a recent cost-radius tradeoo construction which yields less tree cost (and signal delay) for given tree radius bounds than the method of 3]. Our results indicate that the LDT algorithm is hi...

We analyze the impact of wiresizing on the performance of Elmore-based routing constructions. Whereas previous wiresizing schemes are static (i.e., they wiresize an existing topology), we introduce a new dynamic wiresizing technique, which uses wire-sizing considerations to drive the routing construction itself. Simulations show that dynamic wiresiz-ing aaords superior performance over static w...

We present an explicit expression to estimate driving voltage attenuation through RC networks representation of an ultrahigh-speed image sensor. Elmore delay metric for a fundamental RC chain is employed as the first-order approximation. By application of dimensional analysis to SPICE simulation data, we found a simple expression that significantly improves the accuracy of the approximation. Es...

Moments of the impulse response are widely used for interconnect delay analysis, from the explicit Elmore delay (the first moment of the impulse response) expression, to moment matching methods which creates reduced order trans-impedance and transfer function approximations. However, the Elmore delay is fast becoming ineffective for deep submicron technologies, and reduced order transfer functi...

This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to reduce the complexity of the circuits and a preconditioned Krylov-subspace iterative method is then used to perform the nodal analysis on the reduced circuits. By proper selection of the simulation time step and inter...

Elmore delay has been widely used to estimate the interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. For typical RLC interconnections, Elmore delay can deviate signiicantly (by up to 33% or more) from SPICE-computed delay, since it is independent of inductance. We develop an analytical delay model to incorporate inductance eeects into the delay estima...