This paper proposes a novel reversible logic gate, NFT. It is a parity preserving reversible logic gate, that is, the parity of the outputs matches that of the inputs. We demonstrate that the NFT gate can implement all Boolean functions. It renders a wide class of circuit faults readily detectable at the circuit’s outputs. The proposed parity preserving reversible gate, allows any fault that af...

Fault tolerance plays a major role in quantum computer design. As the quantum environment is not stable enough when the information is read from it, better designs with error correcting capability have to be designed to overcome the information loss due to decoherence in quantum circuits. This paper presents one such fault tolerant design using a new reversible gate.

We present a scheme of fault-tolerant quantum computation for a local architecture in two spatial dimensions. The error threshold is 0.75% for each source in an error model with preparation, gate, storage, and measurement errors.

This paper describes the fault-tolerant computing research currently active at Stanford University’s Center for Reliable Computing. One focus is on tolerating hardware faults by means of software (software-implemented hardware fault tolerance). This work mainly targets faults caused by radiation induced upsets. An experiment evaluating the techniques that we have developed, is currently running...

Reversible computation plays an important role in the synthesis of circuits having application in quantum computing, low power CMOS design, bioinformatics and nanotechnology-based systems. Conventional logic circuits are not reversible. A reversible circuit maps each input vector, into a unique output vector and vice versa. We demonstrate how the well-known and very useful, Toffoli gate can be ...

In parity preserving reversible circuit, the parity of the input vector must match the parity of the output vector. It renders a wide class of circuit faults readily detectable at the circuit’s outputs. Thus reversible logic circuits that are parity preserving will be beneficial to the development of fault tolerant systems in nanotechnology. This paper presents an efficient realization of well ...

—Reversible logic design has become one of the promising research directions in low power dissipating circuit design in the past few years and has found its application in low power CMOS design, digital signal processing and nanotechnology. This paper presents the efficient design approaches of fault tolerant carry skip adders (FTCSAs) and compares those designs with the existing ones. Variable...

We consider realistic, multiparameter error models and investigate the performance of the surface code for three possible fault-tolerant superconducting quantum computer architectures. We map amplitude and phase damping to a diagonal Pauli “depolarization” channel via the Pauli twirl approximation, and obtain the logical error rate as a function of the qubit T1,2 and state preparation, gate, an...