This work describes a framework for a GSN (Goal Seeking Neuron) Boolean neural network fast prototyping into a user-programmable gate array. This system provides a VHDL language description of the trained network, allowing the direct implementation of the circuit on an academic FPGA (Field-Programmable Gate Array). A GSN software tool was designed to train and simulate a user-defined network, w...

This paper reports on the implementation of an Artificial Neural Network (ANN) on an Atmel AT6005 Field Programmable Gate Array (FPGA). The work was carried out as an experiment in mapping a bit-level, logically intensive application onto the specific logic resources of a fine-grained FPGA. By exploiting the reconfiguration capabilities of the Atmel FPGA, individual layers of the network are ti...

This paper presents architecture design and FPGA implementation for W-CDMA transceiver system. Altera high-density, high-performance programmable logic devices (PLDs) combined with intellectual property (IP) functions and the Quartus II development software provide a complete solution for the wireless communications application. The paper describes how to implement a wideband code division mult...

This chapter describes the design and implementation of a Smart Acoustic Sensor Array (SASA) System consists of a 52 microphone MEMS array embedded in an FPGA (Field Programmable Gate Array) platform with real-time data acquisition, signal processing, and network communication capabilities. The SASA system is evaluated using several case studies in order to demonstrate the versatility and scala...

101 The Design of an SRAM-Based Field-Programmable Gate Array, Part II: Circuit Design and Layout Paul Chow, Soon Ong Seo, Jonathan Rose, Kevin Chung, Gerard P aez-Monz on and Immanuel Rahardja Abstract|Field-Programmable Gate Arrays (FPGAs) are now widely used for the implementation of digital systems and many commercial architectures are available. Although the literature and data books conta...

A biometric system based on the iris recognition is especially an attractive approach for user identification. Implementation of the iris recognition algorithm on FPGA (field programmable gate array) achieving significant reduction in execution time when compared with software implementation. This paper takes a review on selected methods on research of different methods used for Hardware implem...

This work reports a non-pipelined AES (Advanced Encrypted Standard) FPGA (Field Programmable Gate Array) architecture, with low resource requirements. The architecture is designed to work on CBC (Cipher Block Chaining) mode and achieves a throughput of 1.45 Gbps. This implementation is a module of a configuration library for a Cryptographic Reconfigurable Platform (CRP).

⎯ This paper presents a model-based Register Transfer Level (RTL) design of a 4x2 Multiple-Inputs Multiple-Outputs (MIMO)-Orthogonal Frequency Domain Multiplexing (OFDM) wireless communication systems transmitter and its Field Programmable Gate Array (FPGA) implementation. This system provides a maximum of 600 Mbps with 20 meter of propagation distance using 80 MHz baseband bandwidth with 4x2 M...

In this paper, we present a new contribution of FPGAs (Field-Programmable Gate Array) for control of electrical machines. A detailed description of the structure of direct torque control for PMSM drive, a bench test was realized by a prototyping platform, the experimental results obtained show the effectiveness and the benefit of our contribution and the different steps of implementation for th...

In this paper, the design and implementation of a real-time traffic light control system based on Fieldprogrammable Gate Array (FPGA) technology is reported. The traffic light control system is designed with VHDL language. Its function was verified with simulation. After that, the VHDL design was downloaded to FPGA board hardware to verify its function in experiment. The designed traffic light ...