This paper presents a circuit simulator based on look-up table approach for simulation of VLSI digital circuits with emerging devices which currently cannot be simulated with existing commercial simulators. We have used a point relaxation based circuit simulator which is suitable for digital circuits. To validate our circuit simulator, we have simulated standard circuits with MOS devices of SPI...

Multi-gate MOSFETs has shown better results in subthreshold performances. The replacement of SiO2 by high-k dielectric can fulfill the requirements of Multi-gate MOSFETS with scaling trend in device dimensions. The advancement in fabrication technology has also boosted the use of different high K dielectric materials as oxide layer at different places in MOSFET structures. One of the most impor...

In this letter, we present a comparative study of positive bias temperature instability (PBTI) reliability in InxGa1−xAs FinFET with varying Indium (x = 0.53, 0.70) percentage and quantization [bulk, quantum well (QW)]. Due to lower effective transport mass and higher injection velocity, In0.7Ga0.3As QW FinFET provides better performance than In0.53Ga0.47As bulk FinFET. However, stronger quanti...

In this work, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFET and III-V MOSFETs), and subjected to different reliability scenarios (variability and soft errors). FinFET-based circuits show the highest robustness against variability and soft error environments.

A micro-power RFIC front-end, a low-noise amplifier (LNA) combined with a voltage controlled oscillator (VCO), has been designed using FinFET BSIMSOI model, which is developed for all FinFET transistors fabricated at the SPAWAR system center. The LNA power consumption is 26 μW at 0.5V supply and the VCO power consumption is 29 μW at 0.5V supply.

The bulk CMOS technology is expected to scale down to about 32nm node and likely the successor would be the FinFET. The FinFET is an ultra-thin body multi-gate MOS transistor with among other characteristics a much higher voltage gain compared to a conventional bulk MOS transistor [1]. Bandgap reference circuits cannot be directly ported from bulk CMOS technologies to SOI FinFET technologies, b...

The Double Gate FinFET has been designed for 90nm as an alternative solution to bulk devices. The FinFET with independent gate (IDG) structure is designed to control Vth. When the Vth is controlled the leakage current can be decreased by improving its current driving capability. The metal used for the front gate and back gate is TiN. Here the device performance is compared using nitride spacer ...

Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS at the nanoscale. FinFETs are double-gate devices. The two gates of a FinFET can either be shorted for higher perfomance or independently controlled for lower leakage or reduced transistor count. This gives rise to a rich design space. This chapter provides an introduction to various interesting FinFET logic des...

By applying appropriate tensor transformations for the subband solutions of electron and hole and their transport properties, we demonstrated the capability of determining the phonon induced mobility for planar and FinFET MOSFET devices under arbitrary stress, wafer and channel orientations. The electron and hole mobilities for such devices are numerically solved and their angular dependences o...