The chief goal of partial scan/BIST selection is to identify the minimum number of flip flops in a design which can be converted into test flip flops to enable high fault coverage. We propose the elimination of reconvergent fanout during partial scan/BIST selection by choosing flip flops on reconvergent fanout paths. We present a partial scan/BIST selection algorithm which minimizes reconvergen...

This paper explores the energy-delay space of eight widely referred flip-flops in a 0.13μm CMOS technology. The main goal has been to find the smallest set of flip-flop topologies to be included in a “high performance” flip-flop cell library covering a wide range of power-performance targets. Based on our comparison results, transmission gate-based flipflops show the best power-performance trad...

Several techniques for choosing state assignments which tend to minimize the combinational input and output circuitry of sequential machines have been developed. One of these techniques is a heuristic scoring approach which was originally developed assuming delays as memory elements [1]. This technique was later expanded to cover the cases when trigger flip-flops or combinations of trigger flip...

survey a set of flip-flops designed for low power and high performance. We highlight the basic features of these flip-flops and evaluate them based on timing characteristics, power consumption, and other metrics.

We demonstrate a procedure for designing CMOS ternary circuits based on a discussion of threshold comparison, transmission, and union Qperations. Using some basic CMOS ternary circuits, we design CMOS ternary flip-flops (tri-flops) such as ternary latch and various master/slave triflops. These tri-flops have two additional binary inverse outputs with a fixed threshold. As examples of sequential...

In digital VLSI system the clock distribution network and flip flops are most power consuming components. The reduction of power consumption by clock distribution networks & flip flop makes the total VLSI system as low power VLSI system. In the earlier VLSI system design, different power consumption methods are followed to design the various flip-flops .The SABFF(sense amplifier based flip flop...

We present a new low-power BIST (built-in-self-test) for sequential circuits. State correlation analysis is first performed on the flip-flop values in the relaxed, compacted sequence for the undetected faults to extract spatial correlations among the flip-flops. The extracted spatial correlation matrix not only provides additional metrics through which the scan order may be altered, but also al...