A parallel structure for a CMOS four-quadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a low-voltage high-performance CMOS four-quadrant analog multiplier is designed and fabricated by 0.8m N-well doublepoly-double-metal CMOS technology. Experimental ...

A CMOS four-quadrant analog multiplier circuit for neural networks integrated circuit implementation is presented. By applying differential balanced current mode signals (both for the input, output and weight signals) the multiplication function is easily implemented through two translinear loops. The multiplier exhibits low power consumption (the dc current is 250 nA under a differential power...

In the proposed multiplier configuration, a new technique is proposed for multiplication of two sampled analog signals and the output is in digital form. One analog signal is fed to the input of first delta-sigma modulator (DSM1) after sampling. The sampled output of the second analog signal is negated or not negated depending on the bit state at the output of DSM1 and is fed to the input of se...

In this paper, a reconfigurable, low power four quadrant memristor and carbon nanotube field effect Transistor (CNFET) based analog multiplier is proposed. The circuit is verified by extensive HSPICE simulations using experimentally verified memristor and Stanford CNFET models that have been calibrated for 90% accuracy at the 32nm technology node. The proposed multiplier has an input range of ±...

A four-quadrant CMOS analog multiplier is presented. The device is nominafly biased with +5-V supplies, has identicaf full-scafe single-ended x and y inputs of +4 V, and exhibits less than 0.5 percent Manuscript received March 1, 1987; revised July 18, 1987. The authors are with the Department of Electrical Engineering, Texas A&M University, College Station, TX 77843-3128. IEEE Log Number 87168...

A new cascadable CMOS based voltage squarer circuit having voltage input/current output and its analog four-quadrant multiplier application are presented. The proposed structure has high input impedance and high output impedance; thus, it can be easily connected to other circuits without requiring any extra buffers. Moreover, its two symmetrical bias voltages have high input impedances; accordi...

Abstract A four-quadrant analog multiplier using a novel type of GaAs transistor is presented. This device, called 2-D MESFET, is dedicated to low power and high speed applications[1],[2]. A special architecture for the multiplier was designed by taking advantage of the dual-gate structure of the 2-D MESFET. The circuit relies on the square algebraic identity [8], with the squaring operation re...

The floating-gate transistor can be used to design analog circuits, such as current mirrors [1], current scaler[2] and current multiplier [3, 4] and divider [4]. The multiple input floating-gate transistor can be used to design ultra lowvoltage “pseudo differential” pairs [1], hence ULV rail-to-rail amplifiers and analog multipliers are feasible using the floating-gate technique. In this paper ...