The defects related to the gate–dielectric in high-j-MOSFETs are studied using the 1/f noise technique. Three different types of gate electrodes were used for this purpose – poly-Si, metal (TiN/TaN) and fully Ni Silicided (FUSI) electrodes with Hf-based oxides as the gate dielectric layer. All the three types of devices show a specific behavior near the gate electrode–dielectric interface when ...

Ultrathin Hf-Ti-O higher k gate dielectric films (~2.55 nm) have been prepared by atomic layer deposition. Their electrical properties and application in ETSOI (fully depleted extremely thin SOI) PMOSFETs were studied. It is found that at the Ti concentration of Ti/(Ti + Hf) ~9.4%, low equivalent gate oxide thickness (EOT) of ~0.69 nm and acceptable gate leakage current density of 0.61 A/cm2 @ ...

In this paper, we propose and validate a novel design for a double-gate tunnel fi eld-effect transistor (DG Tunnel FET), for which the simulations show significant improvements compared with single-gate devices using an SiO2 gate dielectric. For the fi rst time, DG Tunnel FET devices, which are using a high-κ gate dielectric, are explored using realistic design parameters, showing an ON-current...

LI, WENMEI. Characterization of High-κ Gate Stacks in Metal-Oxide-Semiconductor Capacitors. (Under the direction of Dr. Dennis M. Maher) The purpose of this research has been to use off-line characterization techniques to establish material-specific properties of gate-stack constituents (i.e., high-κ dielectric stacks and electrodes) and complete gate-stack structures. Hence, the characterizati...

A dual-halo dual-dielectric triple-material cylindrical-gate-all-around/surrounding gate (DH-DD-TM-CGAA/SG) MOSFET has been proposed and an analytical model for the transconductance-to-drain current ratio (TDCR) has been developed. It is verified that incorporation of dual-halo with dual-dielectric and triple-material results in enhancing the device performance in terms of improved TDCR. The ef...

The influence of the nature of interface between organic semiconductor and gate dielectric on bias stress electrical stability of n-type C60-based organic field effect transistors (OFETs) was studied. The bias stress induced threshold voltage (Vth) shift was found to depend critically on the OFET device structure: the direction of V(th) shift in top-gate OFETs was opposite to that in bottom-gat...

Reduction of the gate length and gate dielectric thickness in complementary metal oxide semiconductor (CMOS) transistors for higher performance and circuit density aggravates problems such as poly-silicon (poly-Si) gate depletion, high gate resistance, and dopant penetration from doped poly-Si gate. To alleviate these problems in nanoscale transistors, there is immense interest in the replaceme...

Article history: Received 25 May 2015 Received in revised form 23 June 2015 Accepted 29 June 2015 Available online xxxx

Dual Metal Gate (DMG) technology was proposed to reduce the short channel effects (SCE’s) of double gate MOSFETs. But, DMG alone is not enough to rectify the problem of gate tunneling current due to thinning of oxide layer with device downscaling. So, the use of high-k dielectric as gate oxide is considered to overcome the gate tunneling effect. But, high gate dielectric thickness leads to high...