This paper discusses the type of capacitances for Single Gate MOSFET and Double Gate MOSFET including their quantity. The effect of parasitic capacitance makes double gate MOSFET more suitable component for the designing of digital logic switches than single gate MOSFET. Here, we introducing Independent double gate MOSFET operation based on VeSFET concept. Then introducing with the total capaci...

In this paper, a brief overview of TID effect in SOI technology is presented. The introduction of buried oxide(BOX) adds vulnerability to TID effect in SOI transistors because of its large thickness. Also the BOX introduces special charge traps, the delocalized spin centers, which in most cases are positive. The charge buildup in BOX could increase the leakage current in front gate transistor i...

In this paper, we propose a new heterostructure dual material gate junctionless field-effect transistor (H-DMG-JLFET), with negative differential resistance (NDR) characteristic. The drain and channel material are silicon and source material is germanium. The gate electrode near the source is larger. A dual gate material technique is used to achieve upward band bending in order to access n-i-p-...

This study investigates geometrical variability on the sensitivity of the junctionless tunneling field effect transistor (JLTFET) and Heterostructure JLTFET (HJLTFET) performance. We consider the transistor gate dielectric thickness as one of the main variation sources. The impacts of variations on the analog and digital performance of the devices are calculated by using computer aided design (...

The Graphene based single electron transistor (SET) as a coulomb blockade device need to be explored .It is a unique device for high-speed operation in a nano scale regime. A single electron transfers via the coulomb barriers, but its movement may be prevented by coulomb blockade, so its effect is investigated in this research. The conditions of coulomb blockade and its controlling factors such...

In this paper review study on different types of Junctionless transistor is promoted. Here a comparative study of SOI, bulk planar, double gate and tunnel Junctionless field effect transistor. It is observed Junctionless transistor exhibits better short channel effects and ON current then inversion mode device. Tunnel Junctionless transistor exhibits the properties of both tunnel FET and Juncti...

The fabrication and measurements of solution-processed vertically stacked complementary organic field-effect transistors (FETs) with a high static noise margin (SNM) are reported. In the device structure, a bottom-gate p-type organic FET (PFET) is vertically integrated on a top-gate n-type organic FET (NFET) with the gate shared in-between. A new strategy has been proposed to maximize the SNM b...

We have fabricated conventional planar transistors of various gate lengths down to as small as 10nm polysilicon gate lengths, in order to examine transistor scaling. At 30nm gate lengths, the devices show excellent device characteristics, indicating that this node can be met with conventional transistor design. At lower gate lengths of 20 and 15nm, the devices still maintain excellent device ch...

Adiabatic logic is an implementation of reversible logic in CMOS where the current flow through the circuit is The dual rail toffoli gate is designed using transmission gate. minimum sized XOR gate is implemented at 0.12ìm. solving the problems. Transmission Gate (TG) uses to realize complex logic functions by using a small number It is implemented in Standard CMOS logic (3). Proposed CLA imple...