In digital VLSI system the clock distribution network and flip flops are most power consuming components. The reduction of power consumption by clock distribution networks & flip flop makes the total VLSI system as low power VLSI system. In the earlier VLSI system design, different power consumption methods are followed to design the various flip-flops .The SABFF(sense amplifier based flip flop...

The choice of flip-flop technologies is an essential importance in design of VLSI integrated circuits for high speed and high performance CMOS circuits. The main objective of this project is to design a Low-Power Pulse-Triggered flip-flop. Flip-flops are the major storage elements in all SOC’s of digital design. They accommodate most of the power that has been applied to the chip. Flip-flop is ...

Power dissipation of IC during test mode is greater than the IC’s normal mode of functioning. Power consumption in scan based testing is high due to the toggling of the combinational logic during the scan shift.In digital systems power reduction is the most critical issue. A FLIP FLOP is a one bit storage device used for storage device used for storage purpose. Mostly used d-flip flop in digita...

In this paper, we examine the problems in the CDN of the flip flop & design an improved CDN oriented Flip-flop which is Clocked Pair Shared Flip Flop (CPSFF). Clock Division Network (CDN)’S plays an important role in the flip flop design and it’s the major element in the flip –flop for producing the logical outputs it’s much important to design the CDN with low power and area. Power consumption...

Power reduction has become a vital design goal for sophisticated design applications, whether mobile or not. dropping power consumption in design enables better, cheaper products to be designed and power-related chip failures to be minimized. Researchers have shown that multi-bit flip-flop is an effective method for clock power consumption reduction. The underlying idea behind multi-bit flip-fl...

New designs for Hybrid latch flip-flip (HLFF) and implicit-pulsed data-close-to-output (ip-DCO) flipflop circuits are proposed to improve the redundant switching activity, speed and power as these flip-flop circuits are basic building blocks of many timing elements. This paper evaluates and compares the performance of various flip-flop circuits which can reduce the effect of redundant switching...

Flip and flop splice variants of AMPA receptor subunits are expressed in distinct but partly overlapping patterns and impart different desensitization kinetics to cognate receptor channels. In the absence of specific antibodies, isoform-specific differences in trafficking or localization of native flip and flop subunits remain uncharacterized. We report that in several transfected cell lines, t...

A novel Single Event Upset (SEU) tolerant flip-flop design is proposed, which is well suited for very-low power electronics that operate in subthreshold (<Vt ≈ 500 mV). The proposed flip-flop along with a traditional (unprotected) flip-flop, a Sense-Amplifier-based Rad-hard Flip-Flop (RSAFF) and a Dual Interlocked storage Cell (DICE) flip-flop were all fabricated in MIT Lincoln Lab’s XLP 0.15 μ...

− This paper describes novel low-power high-speed flip-flop called dual edge-triggered NAND keeper flip-flop (DETNKFF). The flip-flop achieves substantial power reduction by incorporating dual edge-triggered operation and by eliminating redundant transitions. It also minimizes the data-tooutput latency by reducing the height of transistor stack on the critical path. Moreover, DETNKFF allows neg...

In this paper, a low voltage dual-pulse-clock double edge triggered D'flip-flop (DPDET) is proposed. The DPDET flip-flop uses a split output latch clocked by a short pulse train. Compared to the previously reported double edge triggered flip-flops, the DPDET flip-flop uses only six transistors with two transistors being clocked, operating correctly under low supply voltage. The total transistor...