In practical realizations of sequential (or pipelined) A/D converters, some form of redundancy is typically employed to help absorb imperfections in the underlying circuits. The purpose of this paper is to review the various ways in which redundancy has been used in successive approximating register (SAR) ADCs, and to connect findings from the information theory community to ideas that drive mo...

Built-in self-test (BIST) refers to those testing techniques where additional hardware is added to a design so that testing is accomplished without the aid of external hardware. Usually, a pseudo-random generator is used to apply test vectors to the circuit under test and a data compactor is used to produce a signature. To increase the reliability and yield of embedded memories, many redundancy...

This paper describes how a set of off-the-shelf general purpose digital computers is being managed in a redundant avionic configuration while performing flight-critical functions for the Space Shuttle. The description covers the architecture of the redundant computer set, associated redundancy design requirements, and the technique used to detect a failed computer and to identify this failure o...

Paper discusses principles of the redundancy classification for the design of fault tolerant computer systems. The basic functions of classification: definitive, characteristic and predictive are presented. Shown that proposed classification of redundancy posses a substantial predictive power. Proposed classification suits for the analysis of roles of hardware and software to achieve fault tole...

A well known problem in diagnosis is the difficulty of providing correct diagnostic conclusions in light incorrect or missing data. Traditional approaches to solving this problem, as typified in the domains of various complex mechanical systems, validate data by using various kinds of redundancy in sensor hardware. While such techniques are useful, we propose that another level of redundancy ex...

This paper proposes a hardware error checking approach(CCRC)by using redundancy core for multiprocessor system-on-chip (MPSoC) and describes several main error detection methods based on Software-Implemented Hardware Fault Tolerance (SHIF) idea proposed in literatures. The CCRC approach insert some error detection code in high level code, detect the existing of redundancy core in MPSoC, then co...

Fault-tolerant (FT) architectures based on classic spatial and temporal redundancy are used in an increasing number of applications. However, the hardware platforms underlying modern highreliability systems have little resemblance to those that were common when such architectures were devised. The earlier fault models are not necessarily out-of-date (e.g. stuck-at faults still play an important...

The ever growing demands of embedded systems to satisfy high computing performance and cost efficiency lead to the trend of using commercial off-the-shelf hardware. However, due to their highly integrated design they are becoming increasingly susceptible to hardware errors (e.g. caused by radiation-induced soft-errors or wear-out effects). Since such faults cannot be fully prevented, systems ha...

As a consequence of current evolution trend of both software development paradigm and processor architecture, memory operations have become not only more frequent during program execution, but also more expensive in terms of hardware resource usage. A useful phenomenon which can be exploited to optimize memory operations is memory redundancy: loads and stores that have the same effects as previ...