Producing efficient circuits from high-level language descriptions remains a problem. This paper proposes three techniques for improving the quality of circuits generated from high-level Esterel specifications, a synchronous, concurrent language designed to specify control-dominated systems. Together, the three techniques aim to improve the quality of the input to logic synthesis to produce bet...

We describe High-level Library Mapping (HLLM), a technique that permits reuse of complex RT-level databook components (speciically ALUs). HLLM can be used to couple existing databook libraries, module generators and custom-designed components with the output of architectural or behavioral synthesis. In this paper, we deene the problem of high-level library mapping, present some algorithmic form...

This paper presents techniques to integrate the use of variable latency units in a high-level synthesis design methodology. Components used as building blocks (e.g., functional units) in conventional high-level synthesis techniques are assumed to have fixed latency values. Variable latency units exhibit the property that the number of cycles taken to compute their outputs varies depending on th...

This paper presents the detailed survey of the Memory, Power and Temperature optimization techniques in the High Level Synthesis presented in the research literature.

In engineering application heuristics are widely used for discrete optimization tasks. We report two cases (in Dense Wavelength Division Multiplexing and High Level Synthesis), where a recent “intelligent” heuristic (STAGE) performs excellently by learning a value-function of the states. We have found that if a global structure of local minima is found by the function approximator then search t...

This paper describes a new approach to integrate testability consideration into high-level synthesis. The approach is based on an iterative technique for high-level synthesis which utilizes a sequence of design-improvement transformations to generate a register-transfer level design from a VHDL behavioral specification. A testability analysis algorithm is used to analyze the intermediate result...

This tutorial surveys the state of the art in high-level synthesis of digital drcuits. It will be published in Advances in Computers, Volume 35, edited by M. Yovits.