In the present study, a new modelling technique was developed for the modelling and analysis of hyperchaotic systems using an expert system based on wavelet decompositions and the Adaptive Neuro-Fuzzy Inference System (ANFIS). The success and superior properties of this new expert system were shown by applying the hyperchaotic Chen system which is a hyperchaotic system. The obtained expert syst...

In this paper a novel very high performance current mirror is presented. It favorably benefits from such excellent parameters as: Ultra high output resistance (36.9GΩ), extremely low input resistance (0.0058Ω), low output (~0.18V) and low input voltage (~0.18V) operation, very low power consumption (20μW), very low offset current (1pA), ultra wide current dynamic range (150dB), and ultra high a...

Dynamic logic is increasingly becoming a logic type of choice for designs requiring high speed and low area. Charge sharing is one of many problems that may cause failure in dynamic logic circuits due to their low noise immunity. The authors address the charge-sharing noise issue. Specifically, they develop an accurate but tractable model for analyzing charge sharing that avoids costly Hspice s...

This paper describes a novel technique to analyze the effects of supply voltage noise on circuit delay for nanometer VLSI circuits. Scattering parameters are used to analyze the power supply noise and to reduce runtime and memory usage. The interconnections of the power grid are modeled by RLC passive elements, constant voltage and time-varying current sources. A fast and accurate MOS modeling ...

Dynamic logic is increasingly becoming a logic type of choice for designs requiring high speed and low area. Charge sharing is one of many problems that may cause failure in dynamic logic circuits due to their low noise immunity. The authors address the charge-sharing noise issue. Specifically, they develop an accurate but tractable model for analyzing charge sharing that avoids costly Hspice s...

This paper presents a way to enhance the Differential Current-Switch Threshold Logic gate (DCSTL) in order to allow the gate to perform more complex functions. This enhancement is achieved by replacing the MOS-transistors at the dataand threshold mapping bank of the DCSTL gate with neuronMOS transisors. First, we introduce the neuronMOS-enhanced DCSTL gate. Then, the results of HSPICE simulatio...

Examination of the statistical variation of integrated passive components is crucial for designing and characterizing the performance of multichip module (MCM) substrates. In this paper, the statistical analysis of parallel plate capaci-tors with gridded plates manufactured in a multilayer low temperature cofired ceramic (LTCC) process is presented. A set of integrated capacitor structures is f...

In this paper, we present the design and experimental evaluation of an 8-bit adiabatic multiplier with built-in self-test (BIST) logic and an internal single-phase sinusoidal power-clock generator. Both the multiplier and the BIST have been designed in SCALD , a true single-phase adiabatic logic family. In HSPICE simulations with post-layout extracted parasitics, our design functions correctly ...

Two-phase micro-pipeline asynchronous modules show faster performance than common fourphase control systems, but the conventional systems with multi-port modules normally suffer from longer signal paths on stacked C-elements. NOR-based control schemes provide an alternative solution to problems such as propagation delay. This paper presents two modified designs from the common two-phase and alt...

Bridging faults are one of the most commonly observed failure mechanisms in contemporary integrated circuits (ICs). Several defects, such as gate oxide short, shorts between two different nodes may cause bridging faults (BF). BFs are known to cause intermediate logic levels and therefore are hard to detect by logic testing. In this article, we investigate the impact of technology scaling on BF ...