The LyS-FASTPARSE team presents BIST-COVINGTON, a neural implementation of the Covington (2001) algorithm for non-projective dependency parsing. The bidirectional LSTM approach by Kiperwasser and Goldberg (2016) is used to train a greedy parser with a dynamic oracle to mitigate error propagation. The model participated in the CoNLL 2017 UD Shared Task. In spite of not using any ensemble methods...

Single Input Change (SIC) testing has been proposed for robust path delay fault testing. In this letter a new Built-In Self Test (BIST) method for SIC vector generation is presented. The proposed method compares favourably to the previously proposed methods for SIC pattern generation with respect to hardware overhead and time required for completion of the test.

as the urban population increases in major cities of iran, many of them face different issues. in iran, new towns are built and located near cities to absorb their overflow population. golbahar new town was built near mashhad metropolis to reduce demographic, economic, social and physical problems of mashhad, but in practice considering its goals, the town has not been able to reduce the proble...

Reseeding is used to improve fault coverage in pseudo-random testing. Most of the work done on reseeding is based on storing the seeds in an external tester. Besides its high cost, testing using automatic test equipment (ATE) makes it hard to test the circuit while in the system. In this paper, we present a technique for built-in reseeding. Our technique requires no storage for the seeds. The s...

A new inter-core BIST circuits for tri-state buffers: T-BIST mainly consists of simple circuits distributed in the relevant blocks. It can give an excellent test-coverage with a little additional hardware. Its configuration is not specified by each SoC structure, so, it is suitable for a general/reusable testable IP.

Built-In Self-Test for logic circuits or logic BIST is gaining popularity as an effective solution for the test cost, test quality, and test reuse problems. Logic BIST implements most of ATE functions on chip so that the test cost can be reduced through less test time, less tester memory requirement, or even a cheaper tester. Logic BIST applies a large number of test patterns so that more defec...