System performance of Gigabit network hosts can severely be degraded due to interrupt overhead caused by heavy incoming traffic. One of the most popular solutions to mitigate such overhead is interrupt coalescing in which a single interrupt is generated for multiple incoming packets. This is opposed to normal interruption in which an interrupt is generated for every incoming packet. In this pap...

Interrupt coalescing is a proven technique for reducing CPU utilization when processing high IO rates in storage and networking controllers. Virtualization introduces a layer of virtual hardware whose interrupt rate can be controlled by the hypervisor. In this paper, we present the design and implementation of a virtual interrupt coalescing scheme for virtual SCSI hardware controllers in a hype...

−− In this work we have designed and implemented an efficient platform-level interrupt controller for a PXA270 microprocessor-based smart phone. Although current hardware development boards include this type of controllers, for specific applications most of them are costly and include too many interrupt sources that represent a waste for a particular design. For this reason we designed our own ...

Interrupt coalescing is a feature implemented in hardware on many of today’s high-performance network interface cards (NIC). It allows a reception of a group of network frames to be notified to the operating system kernel via a single hardware interrupt, thus reducing the interrupt processing overhead, particularly at high packet rates. However, the delays introduced by interrupt coalescing can...

Embedded systems can fail to operate correctly due to interrupt overload: starvation caused by too many interrupt requests. This paper describes three new techniques, two software-based and one hardware-based, for creating systems that delay or drop excessive interrupt requests before they can overload a processor. Our solutions to the interrupt overload problem have several desirable propertie...

In this paper, we propose a system-level design method for control systems that enables the development of Hardware-implemented interrupt handler. The increasing complexity of control systems has led to a rise in the frequency of interrupts. As a result, the processor load increases, leading to a deterioration in the latency of interrupt processing. To solve these problems, we require dedicated...

Interrupt overhead of high-speed network devices can have a significant negative impact on the performance of traditional operating system. The negative impact is primarily due to interrupt overhead associated with the intense arrival of high-speed network packets. This paper presents models and analytical techniques for capturing the behavior and studying the performance of interrupt-driven ke...

Whole-system virtualization causes interrupt handling to be much more difficult than that of operating systems running directly on the hardware. In particular, interrupt delivery and handling is crucial for timer accuracy, I/O performance, and CPU efficiency, among other facets of the system. Substantial efforts have been undertaken to improve interrupt performance on virtual machines, includin...

This paper introduces a profiler architecture for control systems in system-level design. When designing a control system, we need to consider two things. The first thing is the asynchronous signal coming from sensors and actuators, which is called an interrupt request signal. The second thing is a process that should take a higher priority and be activated by an interrupt request signal, which...