In this article, a new structure is presented for MOS (Metal Oxide Semiconductor)-like junctionless carbon nanotube field effect transistor (MOS-like J-CNTFET), in which dual material gate with different work-functions are used. In the aforementioned structure, the size of the gates near the source and the drain are 14 and 6 nm, respectively, and the work-functions are equal and 0.5 eV less tha...

In this paper, a two-dimensional analytical model of laterally graded-channel triple-metal double-gate Junctionless Field Effect Transistor with hetero dielectric gate oxide stack consisting SiO2 and HfO2 is derived. The illustrates higher drive current better performance against hazardous SCEs HCEs in below 30 nm regime. Parabolic approximation method used here to construct channel potentials ...

In this article, a new structure is presented for MOS (Metal Oxide Semiconductor)-like junctionless carbon nanotube field effect transistor (MOS-like J-CNTFET), in which dual material gate with different work-functions are used. In the aforementioned structure, the size of the gates near the source and the drain are 14 and 6 nm, respectively, and the work-functions are equal and 0.5 eV less tha...

In this paper, electric field distribution of the junctionless dual material surrounding gate MOSFETs (JLDMSG) is developed. Junctionless is a device that has similar characteristics like junction based devices, but junctionless has a positive flatband voltage with zero electric field. In Surrounding gate MOSFETs gate material surrounds the channel in all direction , therefore it can overcome t...

This work demonstrates a feasible single poly-Si gate-all-around (GAA) junctionless fin field-effect transistor (JL-FinFET) for use in one-time programming (OTP) nonvolatile memory (NVM) applications. The advantages of this device include the simplicity of its use and the ease with which it can be embedded in Si wafer, glass, and flexible substrates. This device exhibits excellent retention, wi...

The gate-all-around nanowire transistor, due to its extremely tight electrostatic control and vertical integration capability, is a highly promising candidate for sub-5 nm technology nodes. In particular, the junctionless transistors are scalable with reduced variability avoidance of steep source/drain junction formation by ion implantation. Here dual-gated p-type field effect transistor demons...

A comparative study of the drain breakdown phenomena in junctionless (JL) and inversion mode (IM) pchannel MOSFETs has been investigated experimentally with different VGS, channel widths, and VSUB. In order to explain the dependence of drain breakdown voltages (BVDS) on VGS, 3-D device simulation has been also performed. When the device is turned ON, the BVDS is larger in JL than IM transistors...