In this paper, various designs of low-power full-adder cell are studied. Simulation of these full-adder cells are carried out. The experiments simulate all combinations of input transitions and consequently determine the power consumption for the various full-adder cells. The simulation results highlight the weaknesses and the strengths of the various full-adder cell designs. The high performan...

1-bit full adder circuit is a very important primitive cell in the design of Application Specific Integrated Circuits. This paper presents a novel lowpower multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charging recycling capability, this circuit has no direct connections to power supply nodes and the entire signal gates are...

In this paper, we performed the comparative analysis of power consumption of array multiplier circuit implemented with two adder modules and Self Adjustable Voltage level circuit (SVL). The adder modules chosen were 10 transistorStatic Energy Recovery CMOS adder and 8 transistor CMOS (SERF) circuits. At first, the circuit was simulated with adder modules without applying the SVL circuit. And se...

In design of complex arithmetic logic circuits, ground bounce noise, standby leakage current and leakage power are important and challenging issues in nanometer down scaling. In this paper, a low power, low complex and reduced ground bounce noise full adder design based on pass transistor logic (PTL) is proposed. Basically adder is vital part of complex arithmetic logic circuit in arithmetic op...

In the recent year, many other new circuits are proposed using less number of transistors with less delay and extremely low power requirement. An adder consisting with less transistors don't give full swing outputs for all input combinations and there is difference in output level for various combinations and these circuits have very low driving capabilities. other circuits also are proposed in...

The most fundamental operation of any processor is the addition. For any circuit there are two important parameters that comes into count is high speed and low power consumption. Hence the speed of various modules should be maximized to dominate overall performance. Depending upon these parameters various adders can be invented like Carry Look Ahead Adder(CLA),Carry Skip Adder(CSA) and Ripple C...

Due to the trade-off between power, area and performance, various efforts have been done. This work is also based to reduce the power dissipation of the vlsi circuits with the performance upto the acceptable level. The dominant term in a well designed vlsi circuit is the switching power and low-power design thus becomes the task of minimizing this switching power. So, to design a low-power vlsi...

Arithmetic Logic Unit (ALU) is a heart of microprocessor and microcontroller units that are playing main role in digital computers. By optimizing the ALU circuit in microprocessor and microcontroller highly power efficient digital system can be achieved. The use of low power and high performance sub-blocks like adder and multiplier can reduce the total power dissipation of ALU. So in this paper...

In this paper, the various low power full adder circuits with high speed operation have been analyzed. The adder is the basic building blocks of arithmetic circuits, so a small amount of power or delay reduction leads to greatest power saving or better performance of the circuit. Various design techniques are available for low power high speed full adders. All the adders are simulated using tan...

http: // www.ijesrt.com© International Journal of Engineering Sciences & Research Technology [200] IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY PERFORMANCE ANALYSIS OF A LOW-POWER HIGH-SPEED HYBRID 1-BIT FULL ADDER CIRCUIT AND ITS IMPLEMENTATION Swati Narang Electronics & Communication Engineering, Indira Gandhi Delhi Technical University For Women,India DOI: 10.52...