We present a differential comparator-based switched-capacitor (CBSC) pipelined analog-to-digital converter (ADC) with comparator preset, and comparator delay compensation. Compensating for the comparator delay by digitally adjusting the comparator threshold improves the ADC resolution from 2.5-bit to 7.05-bit. The ADC is manufactured in a 90 nm CMOS technology, with a core area of 0.85 mm 9 0.3...

Chlorine is the most widely used disinfectant worldwide, partially because residual protection is maintained after treatment. This residual is measured using colorimetric test kits varying in accuracy, precision, training required, and cost. Seven commercially available colorimeters, color wheel and test tube comparator kits, pool test kits, and test strips were evaluated for use in low-resourc...

High-speed tree-based 64-bit binary comparator: A New Approach is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison of modified and existing 64-bit binary comparator designs concent...

Version 1, October 1, 2006 A methodology for determining the input referred offset voltage of comparators is presented. This in general is difficult as the output of a comparator is discrete valued. The method relies on a Monte-Carlo-Simulation with certain comparator input values and some postprocessing of the comparator output data. The comparator is always operated in its intended environmen...

A high-speed tree-based 64-bit CMOS binary comparator is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison of modified and existing 64-bit binary comparator designs concentrating on...

High-speed 64-bit binary comparator using two stages with two different logic styles is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison of modified and existing 64-bit binary comp...

215 given k and n, one can choose any value of nz in the range from 2 to n to construct a multiway merging network. However, use of certain values of m results in less delay than others for the same value of n. One choice of the value of m is m = n. In this case, can achieve this time bound for the given value of n, are m = 2' with c < [log, n1. We have also assumed that there are n keys in eac...

Recent technology trends have emphasized low power, single supply operation. The LT1016, although capable of such operation, does not include ground in its input range. As such, it must be biased into its operating common mode range for practical single supply use. A new device, the LT1394, maintains the speed and application civility of its predecessor while including ground in its input opera...

Abstract — The design and various analysis of low power, high speed CMOS dynamic latch comparator is presented. The comparator combines the features of both, the resistive dividing network and differential current sensing comparator. The proposed design will improve the comparator performance by reducing the propagation delay, power dissipation, offset with high ICMR. Simulation results are obt...

High-speed 64-bit binary comparator using two different logic styles is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison of modified and existing 64-bit binary comparator designs c...