This paper focuses on the Norwegian medieval religious buildings called stave churches. The word (meaning ‘post, pole’ in Norwegian) derives from buildings’ post and lintel construction, giving churches their characteristic style. structures display a highly developed tradition of wooden Christian buildings, which during Middle Ages (1050–1500) where most common Norway, number can be estimated ...

We present a new pseudorandom testing algorithm f o r the Built-In Self-Test (BIST) of DRAM. In this algorithm, test patterns are complemented to generate state-transitions that are needed f o r the detection of coulping faults. A s a result, the number of test patterns required is less than half of the traditional method, while the extra hardware is negligible.

This paper describes three new march tests for multiport memories. A read (or write) port in such a memory consists of an n-bit address register, an n-to-2n-bit decoder (with column multiplexers for the column addresses) and drivers, and a K -bit data register. This approach gives comprehensive fault coverage for both array and multiport decoder coupling faults. It lends itself to a useful BIST...

In this paper a method to obtain harmonic transfer matrices (HTM) from simulated or measured values (signature & signature response) is presented. These matrices subserve a description of complex systems (e.g. RF front-ends) with real properties, which can’t be specified by simple analytic expressions. They afford to give statements about a systems parameter. That’s why HTM are suitable for Bui...

In mixed-mode BIST, deterministic test patterns are generated with on-chip hardware to detect the random-pattern-resistant (r.p.r.) faults that are missed by the pseudo-random patterns. While previous work in mixed-mode BIST has focused on developing hardware schemes for more efficiently encoding a given set of deterministic patterns (generated by a conventional ATPG procedure), the approach ta...

On Compact Test Sets for Multiple Stuck-At Faults for Large Circuits p. 20 Identification of Feedback Bridging Faults with Oscillation p. 25 Delay Fault and Memory Test Defining SRAM Resistive Defects and Their Simulation Stimuli p. 33 Vector-Based Functional Fault Models for Delay Faults p. 41 Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers p. 47 March Tests for Word-Ori...

In this paper we present a microprocessor-based approach suitable for embedded flash memory testing in a System-on-achip (SOC) environment. The main novelty of the approach is the high flexibility, which guarantees easy exploitation of the same architecture to different memory cores. The proposed approach is compatible with the P1500 standard. A case study has been developed and demonstrates th...

SDRAM (Synchronous Dynamic Random Access Memory) demand has grown exponentially since the 1980s, as a result of technological factors and new areas of application, particularly concerning communication and consumer electronics. The SDRAM market represented in 2007 c. 20% of the total semiconductor business and is seen as a strategic area, justifying private and public investment in the western ...

We have developed an algorithm by which to enable conventional microprocessors to test their on-chip SRAM using their existing hardware and software resources. This test method utilizes a mixture of existing memory testing techniques, which cover all important memory faults. This i; achieved by writing a routine called BIST Program by which only uses the existing ROM and creates no additional h...