This article presents a K-band CMOS voltage controlled oscillator (VCO) using a wide tuning range MOSFET varactor. The proposed varactor consists of a MOSFET in which the source and drain are connected to each other through a large resistor, the body is grounded through another large resistor, and the gate and source are connected through a capacitor. The newly proposed varactor improves the tu...

In this paper, we introduce an application-specific device modeling methodology to develop simple device model that accurately tracks the actual device I-V characteristics in relevant but bounded operating regions. We have specifically used a simple MOSFET model to precisely analyze the switching noises generated on a chip due to simultaneous driving of chip output pads by bulky buffer gates. P...

channel effects are included in the model. In this model, charge conservation holds and channel charge partitioning are properly treated. The simulation results clearly show the importance of 2-11 field-induced effects to short-channel MOS devices. Comparison of the simulated results with reported experimentally measured data shows that the proposed model is far more reliable than the analytica...

There are two dynamics issues in vision chips: (i) The temporal! dynamics issue due to the parasitic capacit,ors in a CMOS chip, and (ii) the spatial dynamics issue due t,o the regular array of processing elements in a chip. These issues are discussed in [l: 2, 31 for the resistor network with only associated parasitic capacitances. However, in this paper we consider also parasitic inductances ...

in biaxially strained p-mosfet with si channel, formation of a parasitic parallel channel due to misalignment of energy bands degrades device performance by increasing off-state current. in this paper a new approach has been introduced to eliminate this parasitic channel by increasing the dopant concentration of virtual substrate up to . using simulation the impact of this method on the parasit...

The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin (1.4 nm) that its leakage current is too large. It is necessary to replace the SiO2 with a physically thicker layer of oxides of higher dielectric constant (κ) or ‘high K’ gate oxides such as hafnium oxide and hafnium silicate. Little was know...

CMOS analogue filters can be implemented with several structures including active-RC, transconductance-C, MOSFET-C, and LC filters. CMOS LC filters have the advantage of being less sensitive to parasitic capacitances as they can actually be absorbed into the total reactance required for the design frequency [1]. This enables them to be utilized in gigahertz range applications; however, on-chip ...

A DC-DC step-up micro power converter for solar energy harvesting applications is presented. The circuit is based on a switchedcapacitor voltage tripler architecture with MOSFET capacitors, which results in an area approximately eight times smaller than using MiM capacitors for the 0.13μm CMOS technology. In order to compensate for the loss of efficiency, due to the larger parasitic capacitance...