The paper presents FPGA implementation of a spectral sharpening process suitable for speech enhancement and noise reduction algorithms for digital hearing aids. Booth and Booth Wallace multiplier is used for implementing digital signal processing algorithms in hearing aids. VHDL simulation results confirm that Booth Wallace multiplier is hardware efficient and performs faster than Booth’s multi...

Abstract—In this paper, a novel Chinese abacus multiplier is presented. The architecture of a 4-bit multiplier is demonstrated. The simulation results of our work are compared with the 4-bit Braun array multiplier. The 0.35μm and 0.18μm TSMC CMOS technologies are used in the simulation. The delay time of the abacus multiplier is at least 63% less than that of Braun array multiplier for 0.18μm t...

We designed a VLSI chip of FFT multiplier based on simple Cooly Tukey FFT using a floating-point representation with optimal data length based on an experimental error analysis. The VLSI implementation using HITACHI CMOS 0.18μm technology can perform multiplication of 2 to 2 digit hexadecimal numbers 19.7 to 34.3 times (25.7 times in average) faster than software FFT multiplier at an area cost ...

Physical limitations of Complementary Metal-Oxide-Semiconductors (CMOS) technology at nanoscale and high cost of lithography have provided the platform for creating Quantum-dot Cellular Automata (QCA)-based hardware. The QCA is a new technology that promises smaller, cheaper and faster electronic circuits, and has been regarded as an effective solution for scalability problems in CMOS technolog...

Almost multiplier is rather a new concept in the theory of almost functions. In this paper we discussion the boundedness of almost multipliers on some special Banach algebras, namely stable algebras. We also define an adjoint and extension for almost multiplier.

Digital multipliers are most widely used component in applications such as convolution, Fourier transform, discrete cosine transforms, and digital filtering. Because outturn of these applications mainly depends on multiplier speed, therefore multipliers must be designed efficiently. In the proposed architecture, a variable-latency multiplier design with novel AHL architecture and a razor flip f...

Formal and informal modifications to the US-Japan Alliance have expanded value operational structure delivers in support of US Japanese national combined naval activities Southeast Asia. This article analyzes how now serves as an increasingly powerful force multiplier which magnifies capabilities, efficiency, impact two allies’ Unlike previous studies on role United States or Japan region, it f...