Network on Chip (NoC) is an enabling methodology of integrating a very high number of intellectual property (IP) blocks in a single System on Chip (SoC). A major challenge that NoC design is expected to face is the intrinsic unreliability of the interconnect infrastructure under technology limitations. Research must address the combination of new device-level defects or error-prone technologies...

There are two dynamics issues in vision chips: (i) The temporal dynamics issue due to the parasitic capacitors in a CMOS chip, and (ii) the spatial dynamics issue due to the regular array of processing elements in a chip. These issues are discussed in [1]–[3] for the resistor network with only associated parasitic capacitances. However, in this paper we consider also parasitic inductances as we...

In this paper, we describe new vision chip architecture, which enables simultaneous output of multi-target positions. This architecture selects targets that don’t overlap at each other in the direction of the column and extracts the target positions simultaneously. Thanks to this simultaneous output, the vision chip based on the architecture can obtain many target positions at high-speed. On th...

There has been a recent upsurge of interest in applying Code Division Multiple Access (CDMA) techniques to optical networks. Conventional spreading codes for OCDMA, known as optical orthogonal codes (OOC) spread the signal in the time domain only, which often results in the requirement of a large chip rate. By spreading in both time and wavelength using two-dimensional OOCs, the chip rate can b...

Optical Network-on-Chip (ONoC) is a promising emerging technology, which can solve the bottlenecks faced by electrical on-chip interconnection. However, the existing proposals of ONoC are mostly built on fixed topologies, which are not flexible enough to support various applications. To make full use of the limited resource and provide a more efficient approach for resource allocation, RONoC (R...

With the increasing complexity of Multi-Core System-on-Chip (MCSoC) and its communications requirement, Network-on-Chip (NoC) has emerged as a solution of nonscalable shared bus schemes currently used in MCSoC implementation. Recently, a new NoC structure based on WKrecursive network was analyzed and compared to 2D Mesh structure based on several performance metrics such as packet losses, throu...

In heterogeneous tiled System-on-Chip architectures a Network-on-Chip is used to transport messages between processing elements. A reconfigurable network interface is used to connect the processing elements to the Network-on-Chip, converting the messages between both domains. This paper introduces the Hydra: a network interface for the MONTIUM TP, a coarse-grained reconfigurable processor desig...

Networks on Chip (NoC) has emerged as the paradigm for designing scalable communication architecture for Systems on Chips (SoCs). Avoiding the conditions that can lead to deadlocks in the network is critical for using NoCs in real designs. Methods that can lead to deadlock-free operation with minimum power and area overhead are important for designing application-specific NoCs. The deadlocks th...