This paper uses a CAD methodology proposed by the authors to design a low-power 2ndorder Σ∆M. This modulator has been fabricated in a 0.7μm CMOS technology to be used as the front-end of an energy metering mixed-signal ASIC and features 16.4bit at a digital output rate of 9.6kHz with a power consumption of 1.71mW. It yields a value of the figure which is the smallest reported to now, thus demon...

The placement of substrate contacts in epi and non-epi technologies is analyzed in order to control and reduce the substrate noise amplitude and spreading. The choice of small or large substrate contacts or rings for each of the two major technologies is highlighted. Design guidelines for placing substrate contacts so as to improve the noise immunity of digital circuits in mixed-signal smart-po...

This paper uses a CAD methodology proposed by the authors to design a low-power 2ndorder ΣΔM. This modulator has been fabricated in a 0.7μm CMOS technology to be used as the front-end of an energy metering mixed-signal ASIC and features 16.4bit at a digital output rate of 9.6kHz with a power consumption of 1.71mW. It yields a value of the figure which is the smallest reported to now, thus demon...

The most research on the power consumption of circuits has been concentrated on the switching power and the power dissipated by the leakage current has been relatively minor area. In today’s IC design, one of the key challenges is the increase in power dissipation of the circuit which in turn shortens the service time of battery-powered electronics, reduces the long-term reliability of circuits...

a high accurate and low-voltage analog cmos current divider which operates with a single power supply voltage is designed in 0.18µm cmos standard technology. the proposed divider uses a differential amplifier and transistor in triode region in order to perform the division. the proposed divider is modeled with neural network while tlbo algorithm is used to optimize it. the proposed optimization...

Bell’s Law predicts continual reductions in the size of computing systems. We investigate the status of the next paradigm shift that will usher in ubiquitous computing – submm sensor nodes. However, this form factor remains beyond the capabilities of modern integrated circuit design techniques due to battery size. This paper describes new ultra-low power circuit techniques applied to digital pr...

Integrated circuit design advances into the nanoscale era towards more compact, higher performance and lower power devices. However, the large number of transistors per die has entailed an increase of device variability due to subwavelength lithography and layout complexity impacting manufacturability. Therefore, regular designs has emerged as an alternative cell design style towards more litho...

Bell’s Law predicts continual reductions in the size of computing systems. We investigate the status of the next paradigm shift that will usher in ubiquitous computing – submm3 sensor nodes. However, this form factor remains beyond the capabilities of modern integrated circuit design techniques due to battery size. This paper describes new ultra-low power circuit techniques applied to digital p...

In this paper, we look at different possibilities and advantages of our early proposed hybrid planar and nonradiative dielectric (NRD) guide technology in the design of various millimeter-wave circuits. First of all, an overview of the NRD guide technology progress is presented. It indicates that the hybrid planar/NRD-guide (HP/NRDG) technology provides a straightforward assembly of MMIC circui...