This paper studies the performance of a distributed system which is subject to hardware failures and subsequent repairs. A special type of scheduling called gang scheduling is considered, under which jobs consist of a number of interacting tasks which are scheduled to run simultaneously on distinct processors. The distribution for the number of parallel tasks per job varies with time. Two gang ...

Objects like queue, swap, and test-and-set allow two processes to reach consensus, and are consequently “universal” for a system of two processes. But are there deterministic objects that do not solve 2-process consensus, and nevertheless allow two processes to solve a task that is not otherwise wait-free solvable in read-write shared memory? The answer “no” is a simple corollary of the main re...

In this paper we study the performance of a distributed system that is subject to hardware failures and subsequent repairs. A special type of scheduling called gang scheduling is considered, under which jobs consist of a number of interacting tasks which are scheduled to run simultaneously on distinct processors. Two different gang scheduling policies used to schedule parallel jobs are examined...

This chapter presents a novel, mixed-integer programming model of the flexible flow line problem that minimizes the makespan of a product. The proposed model considers two main constraints, namely blocking processors and sequence-dependent setup time between jobs. We extend two previous studies conducted by Kurz and Askin (2004) and Sawik (2001), which considered only one of the foregoing const...

1-1 1-2 1-3 & 2-1 2-2 2-3 & 3-1 The Earth Simulator System By Shinichi HABATA,* Mitsuo YOKOKAWA† and Shigemune KITAWAKI‡ *Computers Division †National Institute of Advanced Industrial Science and Technology (AIST) ‡Earth Simulator Center, Japan Marine Science and Technology Center The Earth Simulator, developed by the Japanese government’s initiative “Earth Simulator Project,” is a highly paral...

In this paper we model a thread’s throughput, the instruction per cycle rate (IPC rate), running on a general microprocessor as used in common embedded systems. Our model is not limited to a particular microprocessor because our aim is to develop a general model which can be adapted thus fitting to different microprocessor architectures. We include stalls caused by different pipeline obstacles ...

In many parallel applications, network latency causes a dramatic loss in processor utilization. This paper examines software pipelining as a technique for network latency hiding. It quanti es the potential improvements with detailed, instruction-level simulations. The benchmarks used are the Livermore Loop kernels and BLAS Level 1. These were parallelized and run on the instruction-level RISC s...

As processors continue to deliver higher levels of performance and as memory latency tolerance techniques become widespread to address the increasing cost of accessing memory, memory bandwidth will emerge as a major performance bottleneck. Rather than rely solely on wider and faster memories to address memory bandwidth shortages, an alternative is to use existing memory bandwidth more efficient...

This paper is written in honour to A. Hordijk. It establishes product form results for a generic and instructive multi-class tandem queue with blocking, to which A. Hordijk has directly and indirectly contributed. First, a sufficient and necessary product form characterization is provided. Next, three special cases are briefly presented. These illustrate the possibility of product forms despite...

The paper describes several efficient parallel implementations of the one-sided hyperbolic Jacobi-type algorithm for computing eigenvalues and eigenvectors of Hermitian matrices. By appropriate blocking of the algorithms an almost ideal load balancing between all available processors/cores is obtained. A similar blocking technique can be used to exploit local cache memory of each processor to f...