As the size of a transistor continuously scales down, single electron effects become important [1 – 3]. Previously, we have studied charge transport in single-electron quantum dot transistors which have a channel consisting of a silicon dot separated from the source and the drain by two constrictions [4], and in single-electron MOS memories that have a polysilicon dot floating gate stacked on a...

In this paper we present a SPICE-compatible macro model based on three MOS transistors to describe split-gate non-volatile memory (NVM) cell characteristics for various sizes of the gap between the gates. The model has initially been developed based on simulated dc-IV-characteristics of reference cells (floating gate connected to control gate) and was verified later with measurements on referen...

The supply and threshold voltage scaling has been proposed for low-voltage/low-power design [1, 2, 3]. The programmable floating-gate circuits [3, 4] can be used to implement low-voltage/low-power digital circuits. The threshold voltages are shifted using reversed supply voltages and UV-light. The supply voltage may be reduced and the current level is determined by the threshold shift. Before t...

A two-stage CMOS operational amplifier with both, gain-boosting and indirect current feedback frequency compensation performed by means of regulated cascode amplifiers, is presented. By using quasi-floating-gate transistors (QFGT) the supply requirements, the number of capacitors and the size of the compensation capacitors respect to other Miller schemes are reduced. A prototype was fabricated ...

This paper presents a two stage operational transconductance amplifier realized using floating gate MOSFETs in differential inputs. A configuration of two stage operational transconductance amplifier using floating gate MOSFET for low power and low voltage applications is presented. Here we design a two stage operational transconductance amplifier using floating gate MOSFET in HSPICE 180nm CMOS...

A single-electron memory, in which a bit of information is stored by one electron, is demonstrated at room temperature. The memory is a floating gate metal-oxide-semiconductor transistor in silicon with a channel width ( approximately 10 nanometers) smaller than the Debye screening length of a single electron and a nanoscale polysilicon dot ( approximately 7 nanometers by 7 nanometers) as the f...

This paper describes the fabrication, and structural and electrical characterization of a new, aerosolnanocrystal floating-gate FET, aimed at non-volatile memory (NVM) applications. This aerosolnanocrystal NVM device features prograderase characteristics comparable to conventional stacked gate NVM devices, excellent endurance (>lo5 P/E cycles), and long-term non-volatility in spite of a thin bo...

a log-domain current-mode true rms-to-dc converter based on a novel synthesis of a simplified current-mode low pass filter and a two-quadrant squarer/divider is presented. the circuit employs floating gate mos (fg-mos) transistors operating in weak inversion region. the converter features low power(<1.5uw), low supply voltage (0.9v), two quadrant input current, immunity from body effect, low ci...

The floating gate technique (FGT) is a very sensitive method to measure very low level leakage currents in MOS capacitors. This indirect technique requires the precise knowledge of the capacitance of the structure under test. We have studied the impact of the capacitance model (classic or quantum) and of polysilicon gate depletion effect. We have shown that for 7.2 nm thin EEPROM tunnel oxides,...