نتایج جستجو برای: reconfigurable instruction set processor

تعداد نتایج: 740389  

2008
Raghudeep Kannavara Nikolaos G. Bourbakis Apostolos Dollas

This paper presents a detailed architecture and instruction set of the SCAN cryptoprocessor. The SCAN cryptoprocessor is a modified SparcV8 processor architecture with a new instruction set to handle image compression, encryption, and information hiding based on the SCAN methodology. The modules for image compression, encryption, and information hiding are synthesized in reconfigurable logic an...

2006
Nikolaos Vassiliadis George Theodoridis Spiridon Nikolaidis

A previously proposed Reconfigurable Instruction Set Processor (RISP) architecture, which tightly couples a coarse-grain Reconfigurable Functional Unit (RFU) to a RISC processor, is considered. Two architectural enhancements, namely partial predicated execution and virtual opcode are presented. An automated development framework for the introduced architecture is proposed. In order to evaluate ...

2008
Stephan Wong Thijs van As Geoffrey Brown

This paper presents the architectural design of a reconfigurable and extensible Very Long Instruction Word (VLIW) processor. In addition to architectural extensibility, our processor also supports reconfigurable operations. Furthermore, we present an application development framework to optimally exploit the freedom of reconfigurable operations. Because our processor is based on the VEX ISA, we...

2003
Elena Moscu Panainte Koen Bertels Stamatis Vassiliadis

In this paper we present compiler extensions for the Molen programming paradigm, which is a sequential consistency paradigm for programming custom computing machines (CCM). The compiler supports instruction set extensions and register file extensions. Based on pragma annotations in the application code, it identifies the code fragments implemented on the reconfigurable hardware and automaticall...

2012
Minoru Watanabe Paul K. Chu

To the present day, the performance of microprocessors has progressed dramatically. Recently, almost all computer systems use reduced instruction set computer (RISC) architectures. However, about 30 years ago, complex instruction set computer (CISC) architectures were widely used for almost all computer systems. The advantages and successes of RISC architectures are attributable to their simpli...

2002
Girish Venkataramani Suraj Sudhir Mihai Budiu Seth Copen Goldstein

Closely coupling a reconfigurable fabric with a conventional processor has been shown to successfully improve the system performance. However, today’s superscalar processors are both complex and adept at extracting Instruction Level Parallelism (ILP), which introduces many complex issues to the design of a hybrid CPU-RFU system. This paper examines the design of a superscalar processor augmente...

2001
M. Iliopoulos T. Antonakopoulos Marios Iliopoulos Theodore Antonakopoulos

Inefficient resources utilization is met in various embedded communication devices, which are based on standard processor cores and custom hardware modules. This paper addresses the inefficient resources utilization problem in MAC processor designs and presents a solution that is based on reconfigurable processor architecture and on dynamic-static instruction partitioning, depending on medium a...

2014
Mahendra Pratap Singh Manoj Kumar Jain Anupam Chattopadhyay Reiner Hartenstein K. Karuri A. Chattopadhyay S. Kraemer R. Leupers G. Ascheid H. Meyr Philip Garcia Katherine Compton Michael Emily Blem andWenyin Fu W. Ahmed Oliver Schliebusch Gerd Ascheid Andreas Wieferink Rainer Leupers Heinrich Meyr Muhammad Rashid Ludovic Apvrille Damir Kirasic Bertrand Granado Patrick Schaumont Ingrid Verbauwhede Kurt Keutzer Majid Sarrafzadeh Jonathan Rose Abbas El Gamal Alberto Sangiovanni-Vincentelli

A new architecture type that is recently evolving is the reconfigurable architecture which combines the benefits of ASIPs (Application Specific Instruction Set Processors) and FPGAs (Field Programmable Gate Arrays). Reconfigurable computing combines software flexibility with high performance hardware. FPGAs are generally employed to construct a reconfigurable block as it provides an instant tim...

2005
N. Vassiliadis N. Kavvadias G. Theodoridis S. Nikolaidis

In this paper, the architecture of an embedded processor extended with a tightly-coupled coarse-grain Reconfigurable Functional Unit (RFU) is proposed. The efficient integration of the RFU with the control unit and the datapath of the processor eliminate the communication overhead between them. To speed up execution, the RFU exploits Instruction Level Parallelism (ILP) and spatial computation. ...

2008
Satnam Singh David J. Greaves

From silicon to science : the long road to production reconfigurable supercomputing p. 2 The von Neumann syndrome and the CS education dilemma p. 3 Optimal unroll factor for reconfigurable architectures p. 4 Programming reconfigurable decoupled application control accelerator for mobile systems p. 15 DNA physical mapping on a reconfigurable platform p. 27 Hardware BLAST algorithms with multi-se...

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