A self-cascading CMOS circuit for operation in weak inversion is presented. The self-cascoding MOSFET circuit has been shown to exhibit greater than twentY:'fold increase in the output resistance, without paying virtually any penalty in real estate and power consumption. The circuit has been used to increase the gain in the front stage of operational amplifiers, and to obtain improved performan...

This paper presents a high performance switched current memory cell The cell is designed for reduced supply voltages and low power For audio applications an accuracy around bits is mandatory The accuracy of the basic memory cell su ers from channel modulation and clock feedthrough errors The channel length modulation error is reduced by cascoding the memory transistor The high gain of the casco...

After explaining the basic operation of a SiC JFET plus silicon MOSFET cascode circuit, the dynamics of cascode switching will be discussed and the use of a QRR tester to evaluate the reverse-recovery characteristics of a cascode circuit will be explained. A comparison of the cascode’s reverse recovery with that of a SiC MOSFET reveals that the JFET cascode actually performs better than the SiC...

A novel circuit topology for high-gain distributed amplifiers is presented in this study. Based on the conventional distributed architecture, the gain cells are realized by cascading cascode stages for gain enhancement. In addition, the stagger-tuning technique is extensively utilized in the design of the cascode stages as well as the cascaded stages, leading to significant improvement in terms...

In this paper, we propose a multistage transimpedance amplifier (TIA) based on the local negative feedback technique. Compared with conventional global-feedback technique, proposed TIA has advantages of wider bandwidth, and lower power dissipation. The schematic characteristics circuit are described. Moreover, employs inductive peaking to increase bandwidth. is implemented using 65 nm complemen...

This work presents a study of the use of a transistor with a different configuration in the channel region, named GradedChannel (GC), for analog application in current mirror circuits with different architectures: Common-source, Cascode and Wilson. A comparison will be done between current mirrors implemented with standard (uniformly doped) SOI and GC SOI nMOSFETs by using simulation and experi...