Reversible computation is of the growing interests to power minimization having applications in low power CMOS design, quantum computing, optical information processing, DNA computing, bioinformatics and nanotechnology. This paper proposes a novel 4x4 bit reversible Multiplier circuit. It is faster and has lower hardware complexity compared to the existing designs. In addition, the proposed rev...

Reversible circuits are vulnerable to intellectual property and integrated circuit piracy. To show these vulnerabilities, a detailed understanding on how to identify the function embedded in a reversible circuit is crucial. To obtain the embedded function, one needs to know the synthesis approach used to generate the reversible circuit in the first place. We present a machine learning based sch...

In parity preserving reversible circuit, the parity of the input vector must match the parity of the output vector. It renders a wide class of circuit faults readily detectable at the circuit’s outputs. Thus reversible logic circuits that are parity preserving will be beneficial to the development of fault tolerant systems in nanotechnology. This paper presents an efficient realization of well ...

The paper discusses the asymptotic depth of a reversible circuit consisting of NOT, CNOT and 2-CNOT gates. Reversible circuit depth function $D(n, q)$ for a circuit implementing a transformation $f\colon \mathbb Z_2^n \to \mathbb Z_2^n$ is introduced as a function of $n$ and the number of additional inputs $q$. It is proved that for the case of implementing a permutation from $A(\mathbb Z_2^n)$...

We investigate the subclass of reversible functions that are self-inverse and relate them to reversible circuits that are equal to their reverse circuit, which are called palindromic circuits. We precisely determine which self-inverse functions can be realized as a palindromic circuit. For those functions that cannot be realized as a palidromic circuit, we find alternative palindromic represent...

Making a reversible circuit fault-tolerant is much more difficult than classical circuit and there have been only a few works in the area of parity-preserving reversible logic design. Moreover, all of these designs are ad hoc, based on some pre-defined parity preserving reversible gates as building blocks. In this paper, we for the first time propose a novel and systematic approach towards pari...

In this paper, simultaneous reduction of circuit depth and synthesis cost of reversible circuits in quantum technologies with limited interaction is addressed. We developed a cycle-based synthesis algorithm which uses negative controls and limited distance between gate lines. To improve circuit depth, a new parallel structure is introduced in which before synthesis a set of disjoint cycles are ...

In recent years ternary reversible logic has gained more attention because of its enormous potential in different fields, in particular quantum computing. In order for any future technologies to be reliable they must be testable, thus developing testing techniques in this area is of great importance. In this work we propose a new approach for creating an online testable ternary reversible circu...

Testable fault tolerant system design has become vital for many safety critical applications. On the other hand, reversible logic is gaining interest in the recent past due to its less heat dissipating characteristics. Any Boolean logic function can be implemented using reversible gates. This paper proposes a technique to convert any reversible logic gate to a testable gate that is also reversi...

In his 2003 paper"Towards an algebraic theory of Boolean circuits", Lafont notes that the class of reversible circuits over a set of k truth values is finitely generated when k is odd. He cites a private communication for the proof. The purpose of this short note is to make the content of that communication available.