With an aim of ultra-low power operation, membranetype distributed-feedback (DFB) lasers consisting of wirelike active regions are realized with an InP-based high index-contrast waveguide by using benzocyclobutene (BCB) as well as direct boding on a silicon-on-insulator (SOI) substrate. Lateral current injection (LCI) type lasers on a semi-insulating (SI) InP substrate are also presented. Keywo...

We propose a design for high quality factor two-dimensional (2D) photonic crystal cavities on silicon-on-insulator (SOI). A quality factor of up to 1.2×10(7) with a modal volume of 2.35(λ/n)(3) is simulated. A very high quality factor of 200,000 is experimentally demonstrated for a 2D cavity fabricated on SOI.

The backreflection in commonly used grating couplers on silicon-on-insulator (SOI) is not negligible for many applications. This reflection is dramatically reduced in our improved compact grating coupler design, which directs the reflection away from the input waveguide. Realized devices on SOI show that the reflection can be reduced down to -50 dB without an apparent transmission penalty.

This letter investigates hot-carrier-induced degradation on 0.1 m partially depleted silicon-on-insulator (SOI) nMOSFETs at various ambient temperatures. The thermal impact on device degradation was investigated with respect to body-contact nMOSFETs (BC-SOI) and floating-body SOI nMOSFETs (FB-SOI). Experimental results show that hot-carrier-induced degradation on drive capacity of FB-SOI device...

Abstarct The work presents the newly deploying technology in semiconductor industry called silicon on insulator (SOI). Its two technology partially and fully depleted SOI and describe how these are different from conventional bulk MOS technology, advantages over bulk technology and floating body effect of PD/FD SOI technology, factors effecting floating body such as kink effects in PD SOI, para...

A low-power 435-MHz single-ended low-noise amplifier was implemented in a 0.35-μm silicon on insulator (SOI) CMOS technology. The SOI CMOS LNA has a simulated noise figure of 0.6 dB, input 1-dB compression point of –12.5 dBm, input thirdorder intercept point of –5 dBm, and small-signal gain of 22 dB. Total power dissipation is 10 mW from a 2.5-V supply. LNA chip area is 1.4 mm x 0.58 mm. Due to...

We present a silicon-on-insulator (SOI) pass-transistor logic (PTL) gate with an active body bias control circuit and compare the proposed PTL gate with other types of PTL gates with different body bias circuits in two different 0.13μm SOI CMOS technologies. The experimental results show that the proposed SOI PTL gate using the body bias controlled technique is superior in terms of performance ...

The silicon-on-insulator (SOI) CMOS technology has a number of advantages over the standard bulk CMOS technology, such as no latch-up effect, high speed and low power. The fully depleted SOI (FD-SOI) technology provided by OKI Electric Industry Co., Ltd. is realizing the full features of the advantages with lowest junction capacitance. Test element group (TEG) structures of transistors were fab...

In this paper an introduction to substrate noise in silicon on insulator (SOI) is given. Differences between substrate noise coupling in conventional bulk CMOS and SOI CMOS are discussed and analyzed by simulations. The efficiency of common substrate noise reduction methods are also analyzed. Simulation results show that the advantage of the substrate isolation in SOI is only valid up to a freq...

Silicon-on-insulator ~SOI! has proven to be a viable alternative to traditional bulk silicon for fabrication of complementary metal–oxide–semiconductor devices. However, a number of unusual phenomena with regards to diffusion and segregation of dopants in SOI have yet to be explained. In the present study, SOITEC wafers were thinned to 700 and 1600 Å using oxidation and etching. Ion implantatio...