A novel heating technique, electromagnetic induction heating (EMIH), uses electromagnetic radiation, ranging in frequency from a few megahertz to tens of gigahertz, to volumetrically heat silicon above 1000 C in only a few seconds. Typical power requirements fall between 900 to 1300 W for silicon wafers 75 to 100 mm in diameter. This technique has successfully produced direct silicon wafer-to-w...

High sensitivity acoustic transducers (microphones) have been fabricated on 5” wafers in a production environment and the experimental results are presented. One of the main advantage of this microphone design is that it can be fabricated on a single wafer eliminating the need for the multiple wafers and subsequent wafers bonding steps as in conventional designs. The devices use thin (~3μm) P+ ...

Surface roughness is one of the crucial factors in silicon fusion bonding. Due to the enhanced surface roughness, it is almost impossible to bond wafers after KOH etching. This also applies when wafers are heavily doped, have a thick LPCVD silicon nitride layer on top or have a LPCVD polysilicon layer of poor quality. It has been demonstrated that these wafers bond spontaneously after a very br...

Silicon direct bonding (SDB) is a bonding technique of two silicon wafers together with homogeneous or heterogeneous layers without the use of any intermediate adhesives. The SDB technique simplifies the process and cost by reducing mask level, and its necessity has increased in terms of its fields of applications such as power devices, SOI, sensors and actuators. Factors which can affect direc...

This paper introduces a photoluminescence-based technique for determining the acceptor concentration in silicon wafers by measuring the formation rate of iron-acceptor pairs. This rate is monitored by bandto-band photoluminescence in low injection, the intensity of which is proportional to the carrier lifetime. The technique is demonstrated with an iron-implanted float zone silicon wafer, heavi...

The CALICE Electromagnetic CALorimeter (ECAL) will be a silicon-tungsten sampling calorimeter [1] with 30 layers of silicon wafers, each containing an 18×18 array of diode pads, giving 9720 channels to be read out. The signal from each pad is amplified by a Very Front End (VFE) ASIC [2] which multiplexes the signals from 18 pads onto one output line. The silicon wafers and VFE chips are mounted...

This paper presents a new, simple method of measuring the generation lifetime in SOI (silicon-on-insulator) MOSFETS. Lifetime is extracted from the transient characteristics of MOSFET subthreshold current. Using this technique, generation lifetime was mapped across ®nished SIMOX (separation by implantated oxygen) wafers, BESOI (bonded and etchedback SOI) wafers, and UNIBOND wafers. BESOI materi...

In today's traditional electronics such as in computers or in mobile phones, billions of high-performance, ultra-low-power devices are neatly integrated in extremely compact areas on rigid and brittle but low-cost bulk monocrystalline silicon (100) wafers. Ninety percent of global electronics are made up of silicon. Therefore, we have developed a generic low-cost regenerative batch fabrication ...

A technique for resist deposition using a novel fluid ejection method is presented in this paper. An ejector has been developed to deposit photoresist on silicon wafers without spinning. Drop-on-demand coating of the wafer reduces waste and the cost of coating wafers. Shipley 1400-21, 1400-27, 1805, and 1813 resists were used to coat sample 3and 4-in wafers. Later, these wafers were exposed and...

porous silicon layers have been prepared from n-type silicon wafers of (100) orientation. sem, ftir and pl have been used to characterize the morphological and optical properties of porous silicon. the influence of varying etching time in the anodizing solution, on structural and optical properties of porous silicon has been investigated. it is observed that pore size increases with etching tim...