OBJECTIVES The objective of this study was to review software errors known as single event upsets (SEUs) or bit flips due to cosmic rays in epilepsy neurostimulators. MATERIALS AND METHODS A case report of a single event upset or bit flip is discussed; device manufacturers and publicly available data were queried for both incidence and types of error as well as strategies of software error mi...

The use of SRAM based FPGA can provide the benefits of re-programmability, in system programming, low cost and fast design cycle. The single events upset (SEU) in the configuration SRAM due to radiation, change the design's function obliging the use in LHC environment only in the restricted area with low hadrons rate. Since we expect in the Atlas muon barrel an integrated dose of 300 Rads and 5...

This paper describes the attributes and goals for a radiation-hard and high-reliability Field Programmable Gate Array (FPGA). The first Qualified Manufacturer List (QML) radiation-hardened antifuse FPGA, RH1280, is characterized. Its total dose and Single Event Effects (SEEs) are tested and the results are reported. Trade-offs and limitations in Single Event Upset (SEU) hardening are also discu...

This paper presents measurement results of bit error rate (BER) and soft error rate (SER) improvement on 150-nm FD-SOI 7T/14T (7-transistor/14-transistor) SRAM test chips. The reliability of the 7T/14T SRAM can be dynamically changed by a control signal depending on an operating condition and application. The 14T dependable mode allocates one bit in a 14T cell and improves the BER in a read ope...

As technology scales, VLSI performance has experienced an exponential growth. As feature sizes shrink, however, we will face new challenges such as soft errors (single-event upsets) to maintain the reliability of circuits. Recent studies have tried to address soft errors with error detection and correction techniques such as error correcting codes and redundant execution. However, these techniq...

A dedicated high-speed 18 Kbit static memory featuring synchronous mode, parity and dual port access has been designed and fabricated in a quarter micron 3 metals commercial CMOS technology. This SRAM has been designed to be a test vehicle to measure Single Event Upset (SEU) effects on a real circuit. The measurements have been performed at the cyclotron of Louvain-la-Neuve, Belgium, with a pro...

When exposed to an harsh environment in space, high atmosphere or even on earth, Integrated Circuits undergo soft errors. Among these events the most worrying is an electrical upset, so called Single Event Upset (SEU) evidenced in latches. We present here the circuit architecture of a new SEU hardened latch. The hardening is based on an integrated redundancy of the information and a high impeda...

Dedication My thanks go, as always, to my maternal grandparents, to whom this dissertation is dedicated. I am indebted to my maternal grandparents for standing beside me all these years and constantly motivating me in my efforts. I wouldn't have been what I am, without their help. And My thanks go to my supervising professor, Nur A. Touba. v Acknowledgements I wish to thank my advisor, Professo...

The experimental dependence of the single event upset (SEU) cross-section versus linear energy transfer (LET) function in the nanoscale (with feature size less than 100 nm) memories is explained with the proposed recombination-limited charge yield, which is significantly dependent on LET.

Single event upsets (SEU) produced by heavy ions in SOI CMOS SRAM cells were simulated using a mixed-mode approach, that is, two-dimensional semiconductor device simulation by TCAD tool coupled with circuit SPICE simulator. The effects of parasitic BJT and particle strike position on the SOI CMOS SRAM cells upset for transistor length scaling from 0.25 um to 65nm are presented.